void __init mach_init_irq(void) { LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR | LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES; mips_cpu_irq_init(); init_i8259_irqs(); bonito_irq_init(); setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction); setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction); }
void __init mach_init_irq(void) { /* init all controller * 0-15 ------> i8259 interrupt * 16-23 ------> mips cpu interrupt * 32-63 ------> bonito irq */ /* Sets the first-level interrupt dispatcher. */ mips_cpu_irq_init(); init_i8259_irqs(); bonito_irq_init(); /* setup north bridge irq (bonito) */ setup_irq(LOONGSON_NORTH_BRIDGE_IRQ, &ip6_irqaction); /* setup source bridge irq (i8259) */ setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ, &cascade_irqaction); }
void __init init_irq_2f(void) { unsigned int mask; /* init all controller * 0-15 ------> i8259 interrupt * 16-23 ------> mips cpu interrupt * 32-63 ------> bonito irq */ /* setup cs5536 as high level trigger */ LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1; LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1); /* Sets the first-level interrupt dispatcher. */ mips_cpu_irq_init(); init_i8259_irqs(); bonito_irq_init(); /* setup north bridge irq (bonito) */ setup_irq(LOONGSON_NORTH_BRIDGE_IRQ, &ip6_irqaction); /* setup source bridge irq (i8259) */ setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ, &cascade_irqaction); }
void __init mach_init_irq(void) { /* init all controller * 0-15 ------> i8259 interrupt * 16-23 ------> mips cpu interrupt * 32-63 ------> bonito irq */ /* most bonito irq should be level triggered */ LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR | LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES; /* Sets the first-level interrupt dispatcher. */ mips_cpu_irq_init(); init_i8259_irqs(); bonito_irq_init(); /* bonito irq at IP2 */ setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction); /* 8259 irq at IP5 */ setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction); }