static int mmc_clk_io_onoff(int sdc_no, int onoff, normal_gpio_cfg *gpio_info, int offset)
{
unsigned int rval;
struct sunxi_mmc_host* mmchost = &mmc_host[sdc_no];
if(sdc_no == 0)
{
boot_set_gpio((void *)gpio_info, 8, 1);
}
else // if(sdc_no == 2)
{
boot_set_gpio((void *)(gpio_info + offset), 8, 1);
}
/* config ahb clock */
rval = readl(mmchost->hclkbase);
rval |= (1 << (8 + sdc_no));
writel(rval, mmchost->hclkbase);
rval = readl(mmchost->hclkrst);
rval |= (1 << (8 + sdc_no));
writel(rval, mmchost->hclkrst);
/* config mod clock */
writel(0x80000000, mmchost->mclkbase);
mmchost->mclk = 24000000;
dumphex32("ccmu", (char*)CCMM_REGS_BASE, 0x100);
dumphex32("gpio", (char*)PIOC_REGS_BASE, 0x100);
dumphex32("mmc", (char*)mmchost->reg, 0x100);
return 0;
}
static int mmc_clk_io_onoff(int sdc_no, int onoff, const normal_gpio_cfg *gpio_info, int offset)
{
unsigned int rval;
struct sunxi_mmc_host* mmchost = &mmc_host[sdc_no];
if(sdc_no == 0)
{
/*
1. change the initial status of gpio-f;
2. change the bias voltage of gpio-f to 3.0V
*/
*(volatile unsigned int *)(0x06000800 + 0xB4) = 0x111111; //CFG0
*(volatile unsigned int *)(0x06000800 + 0xD0) = 0x555; //PULL0
*(volatile unsigned int *)(0x06000800 + 0xC4) = 0x3F; //DATA
__msdelay(5);
*(volatile unsigned int *)(0x06000800 + 0xC4) = 0x0;
__msdelay(5);
*(volatile unsigned int *)(0x06000800 + 0xC4) = 0x3F;
__msdelay(5);
*(volatile unsigned int *)(0x06000800 + 0x314) = 0xA; //BIAS
boot_set_gpio((void *)gpio_info, 8, 1);
}
else // if(sdc_no == 2)
{
boot_set_gpio((void *)(gpio_info + offset), 8, 1);
}
/* config ahb clock */
rval = readl(mmchost->hclkbase);
rval |= (1 << 8);
writel(rval, mmchost->hclkbase);
rval = readl(mmchost->hclkrst);
rval |= (1 << 8);
writel(rval, mmchost->hclkrst);
rval = readl(mmchost->commreg);
rval |= (1<<16)|(1<<18);
writel(rval, mmchost->commreg);
/* config mod clock */
writel(0x80000000, mmchost->mclkbase);
mmchost->mclk = 24000000;
dumphex32("ccmu", (char*)CCMM_REGS_BASE, 0x100);
dumphex32("gpio", (char*)PIOC_REGS_BASE, 0x100);
dumphex32("mmc", (char*)mmchost->reg, 0x100);
return 0;
}
/*
************************************************************************************************************
*
* function
*
* name :
*
* parmeters :
*
* return :
*
* note :
*
*
************************************************************************************************************
*/
void sunxi_serial_init(int uart_port, void *gpio_cfg, int gpio_max)
{
u32 reg, i;
u32 uart_clk;
if( (uart_port < 0) ||(uart_port > 0) )
{
return;
}
//reset
reg = readl(CCMU_BUS_SOFT_RST_REG4);
reg &= ~(1<<(CCM_UART_PORT_OFFSET + uart_port));
writel(reg, CCMU_BUS_SOFT_RST_REG4);
for( i = 0; i < 100; i++ );
reg |= (1<<(CCM_UART_PORT_OFFSET + uart_port));
writel(reg, CCMU_BUS_SOFT_RST_REG4);
//gate
reg = readl(CCMU_BUS_CLK_GATING_REG3);
reg &= ~(1<<(CCM_UART_PORT_OFFSET + uart_port));
writel(reg, CCMU_BUS_CLK_GATING_REG3);
for( i = 0; i < 100; i++ );
reg |= (1<<(CCM_UART_PORT_OFFSET + uart_port));
writel(reg, CCMU_BUS_CLK_GATING_REG3);
//gpio
boot_set_gpio(gpio_cfg, gpio_max, 1);
//uart init
serial_ctrl_base = (serial_hw_t *)(SUNXI_UART0_BASE + uart_port * CCM_UART_ADDR_OFFSET);
serial_ctrl_base->mcr = 0x3;
uart_clk = (24000000 + 8 * UART_BAUD)/(16 * UART_BAUD);
serial_ctrl_base->lcr |= 0x80;
serial_ctrl_base->dlh = uart_clk>>8;
serial_ctrl_base->dll = uart_clk&0xff;
serial_ctrl_base->lcr &= ~0x80;
serial_ctrl_base->lcr = ((PARITY&0x03)<<3) | ((STOP&0x01)<<2) | (DLEN&0x03);
serial_ctrl_base->fcr = 0x7;
return;
}
void UART_open( __s32 uart_port, void *uart_ctrl, __u32 apb_freq )
{
__u32 temp=0, i;
__u32 uart_clk;
__u32 lcr;
volatile unsigned int *reg;
port = uart_port;
// config clock
if(port > 7)
{
return ;
}
reg = (volatile unsigned int *)0x01c2006C;
*reg &= ~(1 << (16 + port));
for( i = 0; i < 100; i++ );
*reg |= (1 << (16 + port));
// config uart gpio
// config tx gpio
boot_set_gpio((normal_gpio_cfg *)uart_ctrl, 2, 1);
// Set Baudrate
uart_clk = ( apb_freq + 8*UART_BAUD ) / (16*UART_BAUD);
lcr = UART_REG_LCR(port);
UART_REG_HALT(port) = 1;
UART_REG_LCR(port) = lcr | 0x80;
UART_REG_DLH(port) = uart_clk>>8;
UART_REG_DLL(port) = uart_clk&0xff;
UART_REG_LCR(port) = lcr & (~0x80);
UART_REG_HALT(port) = 0;
// Set Lin Control Register
temp = ((PARITY&0x03)<<3) | ((STOP&0x01)<<2) | (DLEN&0x03);
UART_REG_LCR(port) = temp;
// Disable FIFOs
UART_REG_FCR(port) = 0x06;
}
static int mmc_clk_io_onoff(int sdc_no, int onoff)
{
unsigned int rval;
struct sunxi_mmc_host* mmchost = &mmc_host[sdc_no];
if(sdc_no == 0)
{
#if defined CONFIG_ARCH_SUN9IW1P1
/*
1. change the initial status of gpio-f;
2. change the bias voltage of gpio-f to 3.0V
*/
*(volatile unsigned int *)(0x06000800 + 0xB4) = 0x111111; //CFG0
*(volatile unsigned int *)(0x06000800 + 0xD0) = 0x555; //PULL0
*(volatile unsigned int *)(0x06000800 + 0xC4) = 0x3F; //DATA
__msdelay(5);
*(volatile unsigned int *)(0x06000800 + 0xC4) = 0x0;
__msdelay(5);
*(volatile unsigned int *)(0x06000800 + 0xC4) = 0x3F;
__msdelay(5);
*(volatile unsigned int *)(0x06000800 + 0x314) = 0xA; //BIAS
#endif
boot_set_gpio((void *)BT0_head.prvt_head.storage_gpio, 8, 1);
}
else // if(sdc_no == 2)
{
boot_set_gpio((void *)(BT0_head.prvt_head.storage_gpio + 16), 8, 1);
}
#if defined(CONFIG_ARCH_SUN8IW1P1) || defined(CONFIG_ARCH_SUN8IW3P1) || defined(CONFIG_ARCH_SUN8IW5P1)|| defined(CONFIG_ARCH_SUN8IW6P1) || defined(CONFIG_ARCH_SUN8IW8P1)|| (defined CONFIG_ARCH_SUN8IW7P1) ||(defined CONFIG_ARCH_SUN8IW9P1)
/* config ahb clock */
rval = readl(mmchost->hclkbase);
rval |= (1 << (8 + sdc_no));
writel(rval, mmchost->hclkbase);
rval = readl(mmchost->hclkrst);
rval |= (1 << (8 + sdc_no));
writel(rval, mmchost->hclkrst);
#elif defined(CONFIG_ARCH_SUN7I)|| defined(CONFIG_ARCH_SUN5I)
/* config ahb clock */
rval = readl(mmchost->hclkbase);
rval |= (1 << (8 + sdc_no));
writel(rval, mmchost->hclkbase);
#elif defined(CONFIG_ARCH_SUN9IW1P1)
/* config ahb clock */
rval = readl(mmchost->hclkbase);
rval |= (1 << 8);
writel(rval, mmchost->hclkbase);
rval = readl(mmchost->hclkrst);
rval |= (1 << 8);
writel(rval, mmchost->hclkrst);
rval = readl(mmchost->commreg);
rval |= (1<<16)|(1<<18);
writel(rval, mmchost->commreg);
#else
#error The platform is not seleted
#endif
/* config mod clock */
writel(0x80000000, mmchost->mclkbase);
mmchost->mclk = 24000000;
dumphex32("ccmu", (char*)CCMM_REGS_BASE, 0x100);
dumphex32("gpio", (char*)PIOC_REGS_BASE, 0x100);
dumphex32("mmc", (char*)mmchost->reg, 0x100);
return 0;
}
/*******************************************************************************
*函数名称: Boot0_C_part
*函数原型：void Boot0_C_part( void )
*函数功能: Boot0中用C语言编写的部分的主流程
*入口参数: void
*返 回 值: void
*备 注:
*******************************************************************************/
void main( void )
{
__u32 status;
__s32 dram_size;
int ddr_aotu_scan = 0;
int pwr_en = 0;
__u32 fel_flag;
__u32 boot_cpu=0;
bias_calibration();
timer_init();
sunxi_serial_init( BT0_head.prvt_head.uart_port, (void *)BT0_head.prvt_head.uart_ctrl, 6 );
if( BT0_head.prvt_head.enable_jtag )
{
boot_set_gpio((normal_gpio_cfg *)BT0_head.prvt_head.jtag_gpio, 6, 1);
}
printf("HELLO! BOOT0 is starting!\n");
print_version();
#ifdef CONFIG_ARCH_SUN7I
reset_cpux(1);
#endif
fel_flag = rtc_region_probe_fel_flag();
if(fel_flag == SUNXI_RUN_EFEX_FLAG)
{
rtc_region_clear_fel_flag();
printf("eraly jump fel\n");
goto __boot0_entry_err0;
}
#ifdef CONFIG_BOOT_A15
// printf("BT0_head.boot_head.boot_cpu=0x%x\n", BT0_head.boot_head.boot_cpu);
// if(BT0_head.boot_head.boot_cpu)
// {
// fel_flag = BOOT_A7_FLAG;
// }
// else
// {
// fel_flag = BOOT_A15_FLAG;
// }
/*
boot_cpu 含义
bit0~7 bit8~15
0:不需要保存标志位 1:当前应该切换a15启动
1:通知u-boot保存 0:当前应该切换a7启动
每次从brom读取的boot_cpu只能是0x100或者0
*/
boot_cpu = BT0_head.boot_head.boot_cpu;
pwr_en = BT0_head.boot_head.pwr_en;
if(fel_flag == BOOT_A15_FLAG)
{
rtc_region_clear_fel_flag();
if(boot_cpu == 0x00) //如果原本是a7启动
boot_cpu = 0x101; //a15启动，需要保存标志位
switch_to_a15(pwr_en);
}
else if(fel_flag == BOOT_A7_FLAG)
{
rtc_region_clear_fel_flag();
if(boot_cpu == 0x100) //如果原本是a15启动
boot_cpu = 0x01; //a7启动，需要保存标志位
}
else
{
if(boot_cpu == 0x100)
{
switch_to_a15(pwr_en); //a15启动，不需要保存标志位
}
else
{
boot_cpu = 0x0; //a7启动，不需要保存标志位
}
}
// printf("BT0_head.boot_head.boot_cpu=0x%x\n", BT0_head.boot_head.boot_cpu);
#endif
mmu_setup();
ddr_aotu_scan = 0;
dram_size = init_DRAM(ddr_aotu_scan, (void *)BT0_head.prvt_head.dram_para);
if(dram_size)
{
//mdfs_save_value();
printf("dram size =%d\n", dram_size);
}
else
{
printf("initializing SDRAM Fail.\n");
goto __boot0_entry_err;
}
#if defined(CONFIG_ARCH_SUN9IW1P1)
__msdelay(100);
#endif
#ifdef CONFIG_ARCH_SUN7I
check_super_standby_flag();
#endif
status = load_boot1();
printf("Ready to disable icache.\n");
mmu_turn_off( ); // disable instruction cache
if( status == 0 )
{
//跳转之前，把所有的dram参数写到boot1中
set_dram_para((void *)&BT0_head.prvt_head.dram_para, dram_size, boot_cpu);
printf("Jump to secend Boot.\n");
boot0_jump(CONFIG_SYS_TEXT_BASE); // 如果载入Boot1成功，跳转到Boot1处执行
}
__boot0_entry_err:
#ifdef CONFIG_BOOT_A15
if(!(boot_cpu & 0xff00))
{
boot0_clear_env();
boot0_jump(FEL_BASE);
}
else
{
rtc_region_set_flag(SUNXI_RUN_EFEX_FLAG);
boot0_clear_env();
watchdog_enable();
}
#endif
__boot0_entry_err0:
boot0_clear_env();
boot0_jump(FEL_BASE);
}
//*****************************************************************************
// void jtag_init(uint32 port_id)
// Description: Select different JTAG port and enable JTAG
//
// Arguments: uint32 port_id 1: GPIOB port, 0: GPIOA port
//
// Return Value: None
//*****************************************************************************
void jtag_init(normal_gpio_cfg *jtag_gpio)
{
boot_set_gpio(jtag_gpio, 6, 1);
}
