void brcm_mips_int2_dispatch(struct pt_regs *regs)
{
unsigned int pendingIrqs,pendingIrqs1, shift,irq;
brcm_mips_int2_disable(0);
pendingIrqs = CPUINT1C->IntrW0Status;
gDebugPendingIrq0 = pendingIrqs &= ~(CPUINT1C->IntrW0MaskStatus);
pendingIrqs1 = CPUINT1C->IntrW1Status;
gDebugPendingIrq1 = pendingIrqs1 &= ~(CPUINT1C->IntrW1MaskStatus);
//if (pendingIrqs == HYDRA_UART0_INTR_MASK)
// do_IRQ(BCM_LINUX_UARTA_IRQ, regs);
//else
// printk("unsolicited interrupt!!!\n");
for (irq=1; irq<=32; irq++)
{
shift = irq-1;
if ((0x1 << shift) & pendingIrqs)
{
if (shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_UART0_CPU_INTR_SHIFT)
do_IRQ(BCM_LINUX_UARTA_IRQ, regs);
#ifdef CONFIG_KGDB
else if ((shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_CPU_INTR_SHIFT)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQSTAT) & BCHP_IRQ0_IRQSTAT_ub_MASK)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) & BCHP_IRQ0_IRQEN_ub_MASK) )
{
//printk("@@@@@@@UARTB IRQ %d\n", irq);
do_IRQ(BCM_LINUX_UARTB_IRQ, regs);
}
#endif
else
do_IRQ(irq, regs);
}
}
for (irq = 32+1; irq <= 32+BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_reserved0_SHIFT; irq++)
{
shift = irq - 32 -1;
if ((0x1 << shift) & pendingIrqs1)
do_IRQ(irq, regs);
}
brcm_mips_int2_enable(0);
}
void brcm_mips_int2_dispatch(struct pt_regs *regs)
{
unsigned int pendingIrqs,shift,irq;
brcm_mips_int2_disable(0);
pendingIrqs = INTC->IrqStatus & INTC->IrqMask;
/* IRQs from 1 to 32 - 0 reserved for main IRQ and 60 for timer */
for (irq = 1; irq <= 32; ++irq)
{
shift = irq -1;
if ((0x1 << shift) & pendingIrqs)
{
if (irq == BCM_LINUX_UPG_IRQ) {
if (UPG_INTC->irqstat_l & UPG_INTC->irqen_l & UPG_UA_IRQ) {
do_IRQ(BCM_LINUX_UARTA_IRQ, regs);
}
else if (UPG_INTC->irqstat_l & UPG_INTC->irqen_l & UPG_SCA_IRQ) {
//printk("Calling do_IRQ for SCA, INTC.stats=%08x, INTC.mask=%08x @%08x, called=%x\n",
// INTC->IrqStatus, INTC->IrqMask, &INTC->IrqStatus, doIrqCalled);
//doIrqCalled |=2;
do_IRQ(BCM_LINUX_SCA_IRQ, regs);
}
else if (UPG_INTC->irqstat_l & UPG_INTC->irqen_l & UPG_SCB_IRQ) {
//printk("Calling do_IRQ for SCB, INTC.stats=%08x, INTC.mask=%08x @%08x, called=%x\n",
// INTC->IrqStatus, INTC->IrqMask, &INTC->IrqStatus, doIrqCalled);
//doIrqCalled |= 4;
do_IRQ(BCM_LINUX_SCB_IRQ, regs);
}
else {
do_IRQ(BCM_LINUX_UPG_IRQ, regs);
}
}
else if (irq == BCM_LINUX_DMA_IRQ || irq == BCM_LINUX_MODEM_IRQ)
brcm_dma_dispatch(irq,regs);
else
do_IRQ(irq, regs);
++g_brcm_intc_cnt[shift];
}
}
brcm_mips_int2_enable(0);
}
void brcm_mips_int2_dispatch(struct pt_regs *regs)
{
unsigned int pendingIrqs,pendingIrqs1,pendingIrqs2, shift,irq;
brcm_mips_int2_disable(0);
pendingIrqs = CPUINT1C->IntrW0Status;
pendingIrqs1 = CPUINT1C->IntrW1Status;
pendingIrqs2 = CPUINT1C->IntrW2Status;
#ifdef DEBUG_UARTA_INTR
#ifdef DEBUG_UARTA_INTR_FROM_INT2IRQ
dump_INTC_regs();
#endif
gDebugPendingIrq0 = pendingIrqs &= ~(gDebugMaskW0 = CPUINT1C->IntrW0MaskStatus);
gDebugPendingIrq1 = pendingIrqs1 &= ~(gDebugMaskW1 = CPUINT1C->IntrW1MaskStatus);
gDebugPendingIrq2 = pendingIrqs2 &= ~(gDebugMaskW2 = CPUINT1C->IntrW2MaskStatus);
#endif // DEBUG_UARTA_INTR
for (irq=1; irq<=32; irq++)
{
shift = irq-1;
if ((0x1 << shift) & pendingIrqs)
{
if (shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_UART0_CPU_INTR_SHIFT) {
PRINTK("UART A\n");
do_IRQ(BCM_LINUX_UARTA_IRQ, regs);
}
else if (shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_CPU_INTR_SHIFT
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQSTAT) & BCHP_IRQ0_IRQSTAT_ubirq_MASK)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) & BCHP_IRQ0_IRQEN_ub_irqen_MASK) )
{
PRINTK("UART B\n");
do_IRQ(BCM_LINUX_UARTB_IRQ, regs);
}
else if (shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_CPU_INTR_SHIFT
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQSTAT) & BCHP_IRQ0_IRQSTAT_ucirq_MASK)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) & BCHP_IRQ0_IRQEN_uc_irqen_MASK) )
{
PRINTK("UART C\n");
do_IRQ(BCM_LINUX_UARTC_IRQ, regs);
}
else if (irq == BCM_LINUX_CPU_ENET_IRQ)
{
#ifndef CONFIG_MIPS_BRCM_IKOS
if (*((volatile unsigned long *)0xb0082420) & *((volatile unsigned long *)0xb0082424) & 0x2 )
do_IRQ(BCM_LINUX_CPU_ENET_IRQ, regs);
else
#endif
printk("unsolicited ENET interrupt!!!\n");
}
else
do_IRQ(irq, regs);
}
}
for (irq = 32+1; irq <= 32+32; irq++)
{
shift = irq - 32 -1;
if ((0x1 << shift) & pendingIrqs1)
do_IRQ(irq, regs);
}
for (irq = 64+1; irq <= 64+32; irq++)
{
shift = irq - 64 -1;
if ((0x1 << shift) & pendingIrqs2)
do_IRQ(irq, regs);
}
brcm_mips_int2_enable(0);
}
void brcm_mips_int2_dispatch(struct pt_regs *regs)
{
unsigned int pendingIrqs,pendingIrqs1, shift,irq;
brcm_mips_int2_disable(0);
#ifdef CONFIG_MIPS_BCM7601B_SECOND_CPU
pendingIrqs = CPUINT1C_TP1->IntrW0Status;
gDebugPendingIrq0 = pendingIrqs &= ~(CPUINT1C_TP1->IntrW0MaskStatus);
pendingIrqs1 = CPUINT1C_TP1->IntrW1Status;
gDebugPendingIrq1 = pendingIrqs1 &= ~(CPUINT1C_TP1->IntrW1MaskStatus);
#else
pendingIrqs = CPUINT1C->IntrW0Status;
gDebugPendingIrq0 = pendingIrqs &= ~(CPUINT1C->IntrW0MaskStatus);
pendingIrqs1 = CPUINT1C->IntrW1Status;
gDebugPendingIrq1 = pendingIrqs1 &= ~(CPUINT1C->IntrW1MaskStatus);
#endif
//printk("pending irqs=%x\n",pendingIrqs);
for (irq=1; irq<=32; irq++)
{
shift = irq-1;
if ((0x1 << shift) & pendingIrqs)
{
if (shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_UART0_CPU_INTR_SHIFT) {
do_IRQ(BCM_LINUX_UARTA_IRQ, regs);
}
else if (shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_CPU_INTR_SHIFT) {
if ((*((volatile unsigned long*)BCM_UPG_IRQ0_IRQSTAT) & BCHP_IRQ0_IRQSTAT_ubirq_MASK)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) & BCHP_IRQ0_IRQEN_ub_irqen_MASK) )
{
do_IRQ(BCM_LINUX_UARTB_IRQ, regs);
}
if ((*((volatile unsigned long*)BCM_UPG_IRQ0_IRQSTAT) & BCHP_IRQ0_IRQSTAT_ucirq_MASK)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) & BCHP_IRQ0_IRQEN_uc_irqen_MASK) )
{
do_IRQ(BCM_LINUX_UARTC_IRQ, regs);
}
if ((*((volatile unsigned long*)BCM_UPG_IRQ0_IRQSTAT) & BCHP_IRQ0_IRQSTAT_udirq_MASK)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) & BCHP_IRQ0_IRQEN_ud_irqen_MASK) )
{
do_IRQ(BCM_LINUX_UARTD_IRQ, regs);
}
do_IRQ(irq, regs);
}
else if (irq == BCM_LINUX_CPU_ENET_IRQ)
{
#ifndef CONFIG_MIPS_BRCM_SIM
if (*((volatile unsigned long *)0xb0082420) & *((volatile unsigned long *)0xb0082424) & 0x2 )
do_IRQ(BCM_LINUX_CPU_ENET_IRQ, regs);
else
printk("unsolicited ENET interrupt!!!\n");
#endif
}
else
do_IRQ(irq, regs);
}
}
for (irq = 32+1; irq <= 32+32; irq++)
{
shift = irq - 32 -1;
#if 0 //vincent
//#ifndef CONFIG_MIPS_BRCM_SIM
if (shift == BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IDE_CPU_INTR_SHIFT)
{
unsigned long l2status = *((volatile unsigned long*)BCM_PATA_IRQ_CPU_STATUS);
if (l2status & BCHP_IDE_L2_CPU_STATUS_IDE_PRI_INT_MASK)
{
do_IRQ(BCM_LINUX_PATA_IRQ, regs);
}
}
else
#endif
if ((0x1 << shift) & pendingIrqs1)
do_IRQ(irq, regs);
}
brcm_mips_int2_enable(0);
}
void brcm_mips_int2_dispatch(struct pt_regs *regs)
{
unsigned int pendingIrqs,pendingIrqs1, shift,irq;
brcm_mips_int2_disable(0);
pendingIrqs = CPUINT1C->IntrW0Status;
gDebugPendingIrq0 = pendingIrqs &= ~(CPUINT1C->IntrW0MaskStatus);
pendingIrqs1 = CPUINT1C->IntrW1Status;
gDebugPendingIrq1 = pendingIrqs1 &= ~(CPUINT1C->IntrW1MaskStatus);
//if (pendingIrqs == HYDRA_UART0_INTR_MASK)
// do_IRQ(BCM_LINUX_UARTA_IRQ, regs);
//else
// printk("unsolicited interrupt!!!\n");
for (irq=1; irq<=32; irq++)
{
shift = irq-1;
if ((0x1 << shift) & pendingIrqs)
{
if ((shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_CPU_INTR_SHIFT)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQSTAT) & BCHP_IRQ0_IRQSTAT_ubirq_MASK)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) & BCHP_IRQ0_IRQEN_ub_irqen_MASK) )
{
do_IRQ(BCM_LINUX_UARTA_IRQ, regs);
}
else if (irq == BCM_LINUX_CPU_ENET_IRQ)
{
//if (*((volatile unsigned long *)0xb0082418) & 0x2 )
if (*((volatile unsigned long *)0xb0082420) & *((volatile unsigned long *)0xb0082424) & 0x2 )
do_IRQ(BCM_LINUX_CPU_ENET_IRQ, regs);
else
printk("unsolicited ENET interrupt!!!\n");
}
else if ((shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_CPU_INTR_SHIFT)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQSTAT) & BCHP_IRQ0_IRQSTAT_ucirq_MASK)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) & BCHP_IRQ0_IRQEN_uc_irqen_MASK) )
{
do_IRQ(BCM_LINUX_UARTC_IRQ, regs);
}
else if ((shift == BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_CPU_INTR_SHIFT)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQSTAT) & BCHP_IRQ0_IRQSTAT_uairq_MASK)
&& (*((volatile unsigned long*)BCM_UPG_IRQ0_IRQEN) & BCHP_IRQ0_IRQEN_ua_irqen_MASK) )
{
do_IRQ(BCM_LINUX_UARTB_IRQ, regs);
}
else
do_IRQ(irq, regs);
}
}
for (irq = 32+1; irq <= 32+32; irq++)
{
shift = irq - 32 -1;
if ((0x1 << shift) & pendingIrqs1)
do_IRQ(irq, regs);
}
#if 0
if (g_intcnt++ >= 0xFFFF)
{
g_intcnt = 0;
for (irq = 1; irq <= 32; ++irq)
{
if (m_intc_cnt[irq - 1] != 0)
printk("IRQ[%d] count = %d\n",irq,g_brcm_intc_cnt[irq - 1]);
}
}
#endif
brcm_mips_int2_enable(0);
}
