/* Early setup - runs on TP1 after cache probe */ static void brcmstb_init_secondary(void) { #if defined(CONFIG_BMIPS4380) unsigned long cbr = BMIPS_GET_CBR(); unsigned long old_vec = DEV_RD(cbr + BMIPS_RELO_VECTOR_CONTROL_1); /* make sure the NMI vector is in kseg0 now that we've booted */ DEV_WR_RB(cbr + BMIPS_RELO_VECTOR_CONTROL_1, old_vec & ~0x20000000); #elif defined(CONFIG_BMIPS5000) write_c0_brcm_bootvec(read_c0_brcm_bootvec() & ~0x20000000); #endif brcmstb_ack_ipi(0); write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); /* hw irq lines 3+4 (gfap) goes to tp0 (secondary thread) */ set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5 | ST0_IE); irq_enable_hazard(); }
static irqreturn_t brcmstb_ipi_interrupt(int irq, void *dev_id) { brcmstb_ack_ipi(irq); smp_call_function_interrupt(); return IRQ_HANDLED; }