/* * write (fill) 0 to SONIC data buffer. */ void snc_nec16_zerobuf(struct snc_softc *sc, u_int32_t offset, size_t size) { bus_space_tag_t memt = sc->sc_memt; bus_space_handle_t memh = sc->sc_memh; u_int16_t noffset, onoffset; size_t osize = size; noffset = snc_nec16_select_bank(sc, offset, 0); onoffset = noffset; /* XXX: should check if offset + size < 0x2000. */ if (size > 3) { if (noffset & 3) { size_t asize = 4 - (noffset & 3); bus_space_set_region_1(memt, memh, noffset, 0, asize); noffset += asize; size -= asize; } bus_space_set_region_4(memt, memh, noffset, 0, size >> 2); noffset += size & ~3; size -= size & ~3; } if (size) bus_space_set_region_1(memt, memh, noffset, 0, size); bus_space_barrier(memt, memh, onoffset, osize, BUS_SPACE_BARRIER_WRITE); }
int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) { bus_addr_t entry_addr; bus_size_t gart_idx; u_long pages, max_ati_pages, max_real_pages; int i, j, ret; /* we need to support large memory configurations */ if (dev->sg == NULL) { DRM_ERROR("no scatter/gather memory!\n"); ret = EINVAL; goto error; } if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) { int flags = 0; DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n"); if (gart_info->gart_reg_if == DRM_ATI_GART_IGP) flags |= BUS_DMA_NOCACHE; gart_info->tbl.dma.mem = drm_dmamem_alloc(dev->dmat, gart_info->table_size, PAGE_SIZE, 1, gart_info->table_size, flags, 0); if (gart_info->tbl.dma.mem == NULL) { DRM_ERROR("cannot allocate PCI GART page!\n"); ret = ENOMEM; goto error; } gart_info->tbl.dma.addr = (u_int32_t *)gart_info->tbl.dma.mem->kva; gart_info->bus_addr = gart_info->tbl.dma.mem->map->dm_segs[0].ds_addr; } else { bus_space_set_region_1(gart_info->tbl.fb.bst, gart_info->tbl.fb.bsh, 0, 0, gart_info->table_size); } max_ati_pages = (gart_info->table_size / sizeof(u_int32_t)); max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); pages = (dev->sg->mem->map->dm_nsegs <= max_real_pages) ? dev->sg->mem->map->dm_nsegs : max_real_pages; KASSERT(PAGE_SIZE >= ATI_PCIGART_PAGE_SIZE); for (gart_idx = 0, i = 0; i < pages; i++) { entry_addr = dev->sg->mem->map->dm_segs[i].ds_addr; for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++, entry_addr += ATI_PCIGART_PAGE_SIZE) pcigart_add_entry(gart_info, gart_idx++, entry_addr); } DRM_MEMORYBARRIER(); return (0); error: gart_info->bus_addr = 0; return (ret); }
/* * Set region operations. */ void bs_through_bs_sr_1(bus_space_tag_t t, bus_space_handle_t bsh, bus_size_t offset, u_int8_t value, bus_size_t count) { bus_space_set_region_1(t->bs_base, bsh, offset, value, count); }