Exemple #1
0
static void
le_pci_wrcsr(struct lance_softc *sc, uint16_t port, uint16_t val)
{
	struct le_pci_softc *lesc = (struct le_pci_softc *)sc;

	bus_space_write_2(lesc->sc_regt, lesc->sc_regh, PCNET_PCI_RAP, port);
	bus_space_barrier(lesc->sc_regt, lesc->sc_regh, PCNET_PCI_RAP, 2,
	    BUS_SPACE_BARRIER_WRITE);
	bus_space_write_2(lesc->sc_regt, lesc->sc_regh, PCNET_PCI_RDP, val);
}
Exemple #2
0
static void
le_isa_wrcsr(struct lance_softc *sc, uint16_t port, uint16_t val)
{
	struct le_isa_softc *lesc = (struct le_isa_softc *)sc;

	bus_space_write_2(lesc->sc_regt, lesc->sc_regh, lesc->sc_rap, port);
	bus_space_barrier(lesc->sc_regt, lesc->sc_regh, lesc->sc_rap, 2,
	    BUS_SPACE_BARRIER_WRITE);
	bus_space_write_2(lesc->sc_regt, lesc->sc_regh, lesc->sc_rdp, val);
}
void
sf256pcs_rset(bus_space_tag_t iot, bus_space_handle_t ioh,
    bus_size_t offset, u_int32_t d)
{
	d  = FM_IO_GPIO(FM_IO_PIN1 | FM_IO_PIN2 | FM_IO_PIN3);
	d |= PCS_WREN_OFF | PCS_DATA_OFF | PCS_CLOCK_OFF;

	bus_space_write_2(iot, ioh, offset, d);
	bus_space_write_2(iot, ioh, offset, d);
}
Exemple #4
0
void
imxuart_start(struct tty *tp)
{
        struct imxuart_softc *sc = imxuart_cd.cd_devs[DEVUNIT(tp->t_dev)];
	bus_space_tag_t iot = sc->sc_iot;
	bus_space_handle_t ioh = sc->sc_ioh;

	int s;
	s = spltty();
	if (ISSET(tp->t_state, TS_BUSY)) {
		splx(s);
		return;
	}
	if (ISSET(tp->t_state, TS_TIMEOUT | TS_TTSTOP))
		goto stopped;
#ifdef DAMNFUCKSHIT
	/* clear to send (IE the RTS pin on this shit) is not directly \
	 * readable - skip check for now
	 */
	if (ISSET(tp->t_cflag, CRTSCTS) && !ISSET(sc->sc_msr, IMXUART_CTS))
		goto stopped;
#endif
	if (tp->t_outq.c_cc <= tp->t_lowat) {
		if (ISSET(tp->t_state, TS_ASLEEP)) {
			CLR(tp->t_state, TS_ASLEEP);
			wakeup(&tp->t_outq);
		}
		if (tp->t_outq.c_cc == 0)
			goto stopped;
		selwakeup(&tp->t_wsel);
	}
	SET(tp->t_state, TS_BUSY);

	if (!ISSET(sc->sc_ucr1, IMXUART_CR1_TXMPTYEN)) {
		SET(sc->sc_ucr1, IMXUART_CR1_TXMPTYEN);
		bus_space_write_2(iot, ioh, IMXUART_UCR1, sc->sc_ucr1);
	}

	{
		u_char buf[32];
		int n = q_to_b(&tp->t_outq, buf, 32/*XXX*/);
		int i;
		for (i = 0; i < n; i++)
			bus_space_write_1(iot, ioh, IMXUART_UTXD, buf[i]);
	}
	splx(s);
	return;
stopped:
	if (ISSET(sc->sc_ucr1, IMXUART_CR1_TXMPTYEN)) {
		CLR(sc->sc_ucr1, IMXUART_CR1_TXMPTYEN);
		bus_space_write_2(iot, ioh, IMXUART_UCR1, sc->sc_ucr1);
	}
	splx(s);
}
/* Cold Reset */
static int
fms_reset_codec(void *addr)
{
	struct fms_softc *sc;

	sc = addr;
	bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_CODEC_CTL, 0x0020);
	delay(2);
	bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_CODEC_CTL, 0x0000);
	delay(1);
	return 0;
}
Exemple #6
0
int
depca_isa_probe(struct device *parent, struct cfdata *match, void *aux)
{
	struct isa_attach_args *ia = aux;
	bus_space_tag_t iot = ia->ia_iot;
	bus_space_handle_t ioh;
	bus_space_handle_t memh;
	int rv = 0;

	/* Disallow impossible i/o address. */
	if (ia->ia_iobase != 0x200 && ia->ia_iobase != 0x300)
		return (0);

	/* Map i/o space. */
	if (bus_space_map(iot, ia->ia_iobase, 16, 0, &ioh))
		return 0;

	if (ia->ia_maddr == MADDRUNK ||
	    (ia->ia_msize != 32*1024 && ia->ia_msize != 64*1024))
		goto bad;

	/* Map card RAM. */
	if (bus_space_map(ia->ia_memt, ia->ia_maddr, ia->ia_msize, 0, &memh))
		goto bad;

	/* Just needed to check mapability; don't need it anymore. */
	bus_space_unmap(ia->ia_memt, memh, ia->ia_msize);

	/* Stop the LANCE chip and put it in a known state. */
	bus_space_write_2(iot, ioh, DEPCA_RAP, LE_CSR0);
	bus_space_write_2(iot, ioh, DEPCA_RDP, LE_C0_STOP);
	delay(100);

	bus_space_write_2(iot, ioh, DEPCA_RAP, LE_CSR0);
	if (bus_space_read_2(iot, ioh, DEPCA_RDP) != LE_C0_STOP)
		goto bad;

	bus_space_write_2(iot, ioh, DEPCA_RAP, LE_CSR3);
	bus_space_write_2(iot, ioh, DEPCA_RDP, LE_C3_ACON);

	bus_space_write_1(iot, ioh, DEPCA_CSR, DEPCA_CSR_DUM);

	if (depca_readprom(iot, ioh, NULL))
		goto bad;

	ia->ia_iosize = 16;
	rv = 1;

 bad:
	bus_space_unmap(iot, ioh, 16);
	return (rv);
}
Exemple #7
0
void
geodesc_attach(struct device *parent, struct device *self, void *aux)
{
	struct geodesc_softc *sc = (void *) self;
	struct pci_attach_args *pa = aux;
	uint16_t cnfg, cba;
	uint8_t sts, rev, iid;
	pcireg_t reg;
	extern void (*cpuresetfn)(void);

	reg = pci_conf_read(pa->pa_pc, pa->pa_tag, SC1100_F5_SCRATCHPAD);
	sc->sc_iot = pa->pa_iot;
	if (reg == 0 ||
	    bus_space_map(sc->sc_iot, reg, 64, 0, &sc->sc_ioh)) {
		printf(": unable to map registers at 0x%x\n", reg);
		return;
	}
	cba = bus_space_read_2(sc->sc_iot, sc->sc_ioh, GCB_CBA);
	if (cba != reg) {
		printf(": cba mismatch: cba 0x%x != reg 0x%x\n", cba, reg);
		bus_space_unmap(sc->sc_iot, sc->sc_ioh, 64);
		return;
	}
	sts = bus_space_read_1(sc->sc_iot, sc->sc_ioh, GCB_WDSTS);
	cnfg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, GCB_WDCNFG);
	iid = bus_space_read_1(sc->sc_iot, sc->sc_ioh, GCB_IID);
	rev = bus_space_read_1(sc->sc_iot, sc->sc_ioh, GCB_REV);

	printf(": iid %d revision %d wdstatus %b\n", iid, rev, sts, WDSTSBITS);

#ifndef SMALL_KERNEL
	/* setup and register watchdog */
	bus_space_write_2(sc->sc_iot, sc->sc_ioh, GCB_WDTO, 0);
	sts |= WDOVF_CLEAR;
	bus_space_write_1(sc->sc_iot, sc->sc_ioh, GCB_WDSTS, sts);
	cnfg &= ~WDCNFG_MASK;
	cnfg |= WDTYPE1_RESET|WDPRES_DIV_512;
	bus_space_write_2(sc->sc_iot, sc->sc_ioh, GCB_WDCNFG, cnfg);

	wdog_register(sc, geodesc_wdogctl_cb);
#endif /* SMALL_KERNEL */

#ifdef __HAVE_TIMECOUNTER
	bus_space_write_4(sc->sc_iot, sc->sc_ioh, GCB_TSCNFG, TSC_ENABLE);
	/* Hook into the kern_tc */
	geodesc_timecounter.tc_priv = sc;
	tc_init(&geodesc_timecounter);
#endif /* __HAVE_TIMECOUNTER */

	/* We have a special way to reset the CPU on the SC1100 */
	cpuresetfn = sc1100_sysreset;
}
void
sf256pcpr_write_bit(bus_space_tag_t iot, bus_space_handle_t ioh,
    bus_size_t off, int bit)
{
	u_int16_t data, wren;

	wren  = FM_IO_GPIO_ALL | FM_IO_GPIO_IN(FM_IO_PIN3) | PCPR_WREN_ON;
	data = bit ? PCPR_DATA_ON : PCPR_DATA_OFF;

	bus_space_write_2(iot, ioh, off, PCPR_CLOCK_OFF | wren | data);
	bus_space_write_2(iot, ioh, off, PCPR_CLOCK_ON  | wren | data);
	bus_space_write_2(iot, ioh, off, PCPR_CLOCK_OFF | wren | data);
}
Exemple #9
0
void
icp_mpr_copy_cmd(struct icp_softc *icp, struct icp_ccb *ic)
{

	bus_space_write_2(icp->icp_dpmemt, icp->icp_dpmemh,
	    ICP_MPR_IC + ICP_COMM_QUEUE + 0 * ICP_COMM_Q_SZ + ICP_OFFSET,
	    ICP_DPR_CMD);
	bus_space_write_2(icp->icp_dpmemt, icp->icp_dpmemh,
	    ICP_MPR_IC + ICP_COMM_QUEUE + 0 * ICP_COMM_Q_SZ + ICP_SERV_ID,
	    ic->ic_service);
	bus_space_write_region_4(icp->icp_dpmemt, icp->icp_dpmemh,
	    ICP_MPR_IC + ICP_DPR_CMD, (u_int32_t *)&ic->ic_cmd,
	    ic->ic_cmdlen >> 2);
}
Exemple #10
0
static int
geode_attach(device_t self)
{
	u_int32_t	reg;
	u_int16_t	cnfg, cba;
	u_int8_t	sts, rev, iid;

	/*
	 * The address of the CBA is written to this register
	 * by the bios, see p161 in data sheet.
	 */
	reg = pci_read_config(self, SC1100_F5_SCRATCHPAD, 4);
	if (reg == 0)
		return ENODEV;

	/* bus_space_map(sc->sc_iot, reg, 64, 0, &sc->sc_ioh)) */
	geode_sc.sc_iot = I386_BUS_SPACE_IO;
	geode_sc.sc_ioh = reg;

	cba = bus_space_read_2(geode_sc.sc_iot, geode_sc.sc_ioh, GCB_CBA);
	if (cba != reg) {
		kprintf("Geode LX: cba mismatch: cba 0x%x != reg 0x%x\n", cba, reg);
		return ENODEV;
	}

	/* outl(cba + 0x0d, 2); ??? */
	sts = bus_space_read_1(geode_sc.sc_iot, geode_sc.sc_ioh, GCB_WDSTS);
	cnfg = bus_space_read_2(geode_sc.sc_iot, geode_sc.sc_ioh, GCB_WDCNFG);
	iid = bus_space_read_1(geode_sc.sc_iot, geode_sc.sc_ioh, GCB_IID);
	rev = bus_space_read_1(geode_sc.sc_iot, geode_sc.sc_ioh, GCB_REV);
#define WDSTSBITS "\20\x04WDRST\x03WDSMI\x02WDINT\x01WDOVF"
	kprintf("Geode LX: iid %d revision %d wdstatus %b\n", iid, rev, sts, WDSTSBITS);

	/* enable timer */
	bus_space_write_4(geode_sc.sc_iot, geode_sc.sc_iot, GCB_TSCNFG, TSC_ENABLE);
	cputimer_register(&geode_timer);
	cputimer_select(&geode_timer, 0);

	/* enable watchdog and configure */
	bus_space_write_2(geode_sc.sc_iot, geode_sc.sc_ioh, GCB_WDTO, 0);
	sts |= WDOVF_CLEAR;
	bus_space_write_1(geode_sc.sc_iot, geode_sc.sc_ioh, GCB_WDSTS, sts);
	cnfg &= ~WDCNFG_MASK;
	cnfg |= WDTYPE1_RESET | WDPRES_DIV_512;
	bus_space_write_2(geode_sc.sc_iot, geode_sc.sc_ioh, GCB_WDCNFG, cnfg);
	wdog_register(&geode_wdog);

	return 0;
}
Exemple #11
0
int
imxuartclose(dev_t dev, int flag, int mode, struct proc *p)
{
	int unit = DEVUNIT(dev);
	struct imxuart_softc *sc = imxuart_cd.cd_devs[unit];
	bus_space_tag_t iot = sc->sc_iot;
	bus_space_handle_t ioh = sc->sc_ioh;
	struct tty *tp = sc->sc_tty;
	int s;

	/* XXX This is for cons.c. */
	if (!ISSET(tp->t_state, TS_ISOPEN))
		return 0;

	(*linesw[tp->t_line].l_close)(tp, flag, p);
	s = spltty();
	if (ISSET(tp->t_state, TS_WOPEN)) {
		/* tty device is waiting for carrier; drop dtr then re-raise */
		CLR(sc->sc_ucr3, IMXUART_CR3_DSR);
		bus_space_write_2(iot, ioh, IMXUART_UCR3, sc->sc_ucr3);
		timeout_add(&sc->sc_dtr_tmo, hz * 2);
	} else {
		/* no one else waiting; turn off the uart */
		imxuart_pwroff(sc);
	}
	CLR(tp->t_state, TS_BUSY | TS_FLUSH);

	sc->sc_cua = 0;
	splx(s);
	ttyclose(tp);

	return 0;
}
Exemple #12
0
int 
sun68k_bus_poke(bus_space_tag_t tag, bus_space_handle_t handle,
    bus_size_t offset, size_t size, uint32_t v)
{
	int result;
	label_t	faultbuf;
	
	nofault = &faultbuf; 
	if (setjmp(&faultbuf))
		result = -1;
	else {
		switch(size) {
		case 1:
			bus_space_write_1(tag, handle, offset, (uint8_t)v);
			break;
		case 2:
			bus_space_write_2(tag, handle, offset, (uint16_t)v);
			break;
		case 4:
			bus_space_write_4(tag, handle, offset, (uint32_t)v);
			break;
		default:
			panic("_bus_space_poke: bad size");
		}
		result = 0;
	}

	nofault = NULL;
	return (result);
}
static int
fms_read_codec(void *addr, uint8_t reg, uint16_t *val)
{
	struct fms_softc *sc;
	int i;

	sc = addr;
	/* Poll until codec is ready */
	for (i = 0; i < TIMO && bus_space_read_2(sc->sc_iot, sc->sc_ioh,
		 FM_CODEC_CMD) & FM_CODEC_CMD_BUSY; i++)
		delay(1);
	if (i >= TIMO) {
		printf("fms: codec busy\n");
		return 1;
	}

	/* Write register index, read access */
	bus_space_write_2(sc->sc_iot, sc->sc_ioh, FM_CODEC_CMD,
			  reg | FM_CODEC_CMD_READ);

	/* Poll until we have valid data */
	for (i = 0; i < TIMO && !(bus_space_read_2(sc->sc_iot, sc->sc_ioh,
		 FM_CODEC_CMD) & FM_CODEC_CMD_VALID); i++)
		delay(1);
	if (i >= TIMO) {
		printf("fms: no data from codec\n");
		return 1;
	}

	/* Read data */
	*val = bus_space_read_2(sc->sc_iot, sc->sc_ioh, FM_CODEC_DATA);
	return 0;
}
void
db_bus_write_cmd(db_expr_t addr, bool have_addr, db_expr_t count,
    const char *modif)
{
	db_expr_t datum;
	bus_space_tag_t iot = &iobus_bs_tag; /* XXX */
	bus_space_handle_t ioh;

	if (!have_addr)
		db_error("target address must be specified");

	bus_space_map(iot, addr, 1, 0, &ioh);

	while (db_expression(&datum)) {
		switch (*modif) {
		case 'b':
			bus_space_write_1(iot, ioh, 0, datum);
			break;
		case '\0':
		case 'h':
			bus_space_write_2(iot, ioh, 0, datum);
			break;
		default:
			db_error("bad modifier");
		}
	}
	bus_space_unmap(iot, ioh, 1);
	db_skip_to_eol();
}
Exemple #15
0
void
virtio_write_device_config_2(struct virtio_softc *sc,
			     int index, uint16_t value)
{
	bus_space_write_2(sc->sc_iot, sc->sc_ioh,
			  sc->sc_config_offset + index, value);
}
Exemple #16
0
static void
geode_wdog_reset(struct geode_wdog_softc *sc)
{
	/* set countdown */ 
	bus_space_write_2(sc->sc_gcb_dev->sc_iot, sc->sc_gcb_dev->sc_ioh,
	    SC1100_GCB_WDTO, sc->sc_countdown);
}
Exemple #17
0
void
qlw_write(struct qlw_softc *sc, bus_size_t offset, u_int16_t value)
{
	bus_space_write_2(sc->sc_iot, sc->sc_ioh, offset, value);
	bus_space_barrier(sc->sc_iot, sc->sc_ioh, offset, 2,
	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
}
Exemple #18
0
int
bppopen(dev_t dev, int flags, int mode, struct lwp *l)
{
	int unit = BPPUNIT(dev);
	struct bpp_softc *sc;
	struct lsi64854_softc *lsi;
	uint16_t irq;
	int s;

	if (unit >= bpp_cd.cd_ndevs)
		return ENXIO;
	sc = device_lookup_private(&bpp_cd, unit);

	if ((sc->sc_flags & (BPP_OPEN|BPP_XCLUDE)) == (BPP_OPEN|BPP_XCLUDE))
		return EBUSY;

	lsi = &sc->sc_lsi64854;

	/* Set default parameters */
	sc->sc_hwcurrent = sc->sc_hwdefault;
	s = splbpp();
	bpp_setparams(sc, &sc->sc_hwdefault);
	splx(s);

	/* Enable interrupts */
	irq = BPP_ERR_IRQ_EN;
	irq |= sc->sc_hwdefault.hw_irq;
	bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq);
	return 0;
}
Exemple #19
0
static int
agg_wrcodec(kobj_t obj, void *sc, int regno, u_int32_t data)
{
	unsigned t;
	struct agg_info *ess = sc;

	/* We have to wait for a SAFE time to write addr/data */
	for (t = 0; t < 20; t++) {
		if ((bus_space_read_1(ess->st, ess->sh, PORT_CODEC_STAT)
		    & CODEC_STAT_MASK) != CODEC_STAT_PROGLESS)
			break;
		DELAY(2);	/* 20.8us / 13 */
	}
	if (t == 20) {
		/* Timed out. Abort writing. */
		device_printf(ess->dev, "agg_wrcodec() PROGLESS timed out.\n");
		return -1;
	}

	bus_space_write_2(ess->st, ess->sh, PORT_CODEC_REG, data);
	bus_space_write_1(ess->st, ess->sh, PORT_CODEC_CMD,
	    CODEC_CMD_WRITE | regno);

	return 0;
}
static void
pcib_mbus_hw_cfgwrite(struct pcib_mbus_softc *sc, u_int bus, u_int slot,
    u_int func, u_int reg, uint32_t data, int bytes)
{
	uint32_t addr, ca, cd;

	ca = (sc->sc_info->op_type != MV_TYPE_PCI) ?
	    PCIE_REG_CFG_ADDR : PCI_REG_CFG_ADDR;
	cd = (sc->sc_info->op_type != MV_TYPE_PCI) ?
	    PCIE_REG_CFG_DATA : PCI_REG_CFG_DATA;
	addr = PCI_CFG_ENA | PCI_CFG_BUS(bus) | PCI_CFG_DEV(slot) |
	    PCI_CFG_FUN(func) | PCI_CFG_PCIE_REG(reg);

	mtx_lock_spin(&pcicfg_mtx);
	bus_space_write_4(sc->sc_bst, sc->sc_bsh, ca, addr);

	switch (bytes) {
	case 1:
		bus_space_write_1(sc->sc_bst, sc->sc_bsh,
		    cd + (reg & 3), data);
		break;
	case 2:
		bus_space_write_2(sc->sc_bst, sc->sc_bsh,
		    cd + (reg & 2), htole16(data));
		break;
	case 4:
		bus_space_write_4(sc->sc_bst, sc->sc_bsh,
		    cd, htole32(data));
		break;
	}
	mtx_unlock_spin(&pcicfg_mtx);
}
Exemple #21
0
int
bppintr(void *arg)
{
	struct bpp_softc *sc = arg;
	struct lsi64854_softc *lsi = &sc->sc_lsi64854;
	uint16_t irq;

	/* First handle any possible DMA interrupts */
	if (lsi64854_pp_intr((void *)lsi) == -1)
		sc->sc_error = 1;

	irq = bus_space_read_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR);
	/* Ack all interrupts */
	bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR,
	    irq | BPP_ALLIRQ);

	DPRINTF(("%s: %x\n", __func__, irq));
	/* Did our device interrupt? */
	if ((irq & BPP_ALLIRQ) == 0)
		return 0;

	if ((sc->sc_flags & BPP_LOCKED) != 0)
		wakeup(sc);
	else if ((sc->sc_flags & BPP_WANT) != 0) {
		sc->sc_flags &= ~BPP_WANT;
		wakeup(sc->sc_buf);
	} else {
		selnotify(&sc->sc_wsel, 0, 0);
		if (sc->sc_asyncproc != NULL)
			softint_schedule(sc->sc_sih);
	}
	return 1;
}
Exemple #22
0
int
bppopen(dev_t dev, int flags, int mode, struct proc *p)
{
	int unit = BPPUNIT(dev);
	struct bpp_softc *sc;
	struct lsi64854_softc *lsi;
	u_int16_t irq;
	int s;

	if (unit >= bpp_cd.cd_ndevs)
		return (ENXIO);
	if ((sc = bpp_cd.cd_devs[unit]) == NULL)
		return (ENXIO);

	lsi = &sc->sc_lsi64854;

	/* Set default parameters */
	s = splbpp();
	bpp_setparams(sc, &sc->sc_hwstate);
	splx(s);

	/* Enable interrupts */
	irq = BPP_ERR_IRQ_EN;
	irq |= sc->sc_hwstate.hw_irq;
	bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR, irq);
	return (0);
}
Exemple #23
0
static void
i80321_pci_write_config(device_t dev, int bus, int slot, int func, int reg,
    u_int32_t data, int bytes)
{
	struct i80321_pci_softc *sc = device_get_softc(dev);
	uint32_t addr;

	if (i80321_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
		return;


	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCAR,
	    addr);
	switch (bytes) {
	case 1:
		bus_space_write_1(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR +
		    (reg & 3), data);
		break;
	case 2:
		bus_space_write_2(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR +
		    (reg & 3), data);
		break;
	case 4:
		bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OCCDR, data);
		break;
	default:
		printf("i80321_pci_write_config: Invalid size : %d\n", bytes);
	}

}
Exemple #24
0
int
bppintr(void *arg)
{
	struct bpp_softc *sc = arg;
	struct lsi64854_softc *lsi = &sc->sc_lsi64854;
	u_int16_t irq;

	/* First handle any possible DMA interrupts */
	if (DMA_INTR(lsi) == -1)
		sc->sc_error = 1;

	irq = bus_space_read_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR);
	/* Ack all interrupts */
	bus_space_write_2(lsi->sc_bustag, lsi->sc_regs, L64854_REG_ICR,
			  irq | BPP_ALLIRQ);

	DPRINTF(("bpp_intr: %x\n", irq));
	/* Did our device interrupt? */
	if ((irq & BPP_ALLIRQ) == 0)
		return (0);

	if ((sc->sc_flags & BPP_LOCKED) != 0)
		wakeup(sc);
	else if ((sc->sc_flags & BPP_WANT) != 0) {
		sc->sc_flags &= ~BPP_WANT;
		wakeup(sc->sc_buf);
	}
	return (1);
}
Exemple #25
0
void
virtio_reinit_start(struct virtio_softc *sc)
{
	int i;

	virtio_set_status(sc, VIRTIO_CONFIG_DEVICE_STATUS_ACK);
	virtio_set_status(sc, VIRTIO_CONFIG_DEVICE_STATUS_DRIVER);
	for (i = 0; i < sc->sc_nvqs; i++) {
		int n;
		struct virtqueue *vq = &sc->sc_vqs[i];
		bus_space_write_2(sc->sc_iot, sc->sc_ioh,
				  VIRTIO_CONFIG_QUEUE_SELECT,
				  vq->vq_index);
		n = bus_space_read_2(sc->sc_iot, sc->sc_ioh,
				     VIRTIO_CONFIG_QUEUE_SIZE);
		if (n == 0)	/* vq disappeared */
			continue;
		if (n != vq->vq_num) {
			panic("%s: virtqueue size changed, vq index %d\n",
			      device_xname(sc->sc_dev),
			      vq->vq_index);
		}
		virtio_init_vq(sc, vq);
		bus_space_write_4(sc->sc_iot, sc->sc_ioh,
				  VIRTIO_CONFIG_QUEUE_ADDRESS,
				  (vq->vq_dmamap->dm_segs[0].ds_addr
				   / VIRTIO_PAGE_SIZE));
	}
}
Exemple #26
0
static int
amdpm_smbus_quick(struct amdpm_softc *sc, i2c_op_t op)
{
	uint16_t data = 0;
	int off = (sc->sc_nforce ? 0xe0 : 0);

	/* first clear gsr */
	amdpm_smbus_clear_gsr(sc);

	/* write smbus slave address and read/write bit to register */
	data = sc->sc_smbus_slaveaddr;
	data <<= 1;
	if (I2C_OP_READ_P(op))
		data |= AMDPM_8111_SMBUS_READ;

	bus_space_write_1(sc->sc_iot, sc->sc_ioh,
	    AMDPM_8111_SMBUS_HOSTADDR - off, data);

	/* host start */
	bus_space_write_2(sc->sc_iot, sc->sc_ioh,
	    AMDPM_8111_SMBUS_CTRL - off,
	    AMDPM_8111_SMBUS_GSR_QUICK);	

	return amdpm_smbus_check_done(sc, op);
}
Exemple #27
0
static void
thunder_pcie_write_config(device_t dev, u_int bus, u_int slot,
    u_int func, u_int reg, uint32_t val, int bytes)
{
	uint64_t offset;
	struct thunder_pcie_softc *sc;
	bus_space_tag_t	t;
	bus_space_handle_t h;

	if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) ||
	    (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX))
		return ;

	sc = device_get_softc(dev);

	offset = PCIE_ADDR_OFFSET(bus, slot, func, reg);
	t = rman_get_bustag(sc->res);
	h = rman_get_bushandle(sc->res);

	switch (bytes) {
	case 1:
		bus_space_write_1(t, h, offset, val);
		break;
	case 2:
		bus_space_write_2(t, h, offset, htole16(val));
		break;
	case 4:
		bus_space_write_4(t, h, offset, htole32(val));
		break;
	default:
		return;
	}

}
static void
generic_pcie_write_config(device_t dev, u_int bus, u_int slot,
    u_int func, u_int reg, uint32_t val, int bytes)
{
	struct generic_pcie_core_softc *sc;
	bus_space_handle_t h;
	bus_space_tag_t t;
	uint64_t offset;

	sc = device_get_softc(dev);
	if ((bus < sc->bus_start) || (bus > sc->bus_end))
		return;
	if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) ||
	    (reg > PCIE_REGMAX))
		return;

	offset = PCIE_ADDR_OFFSET(bus - sc->bus_start, slot, func, reg);

	t = sc->bst;
	h = sc->bsh;

	switch (bytes) {
	case 1:
		bus_space_write_1(t, h, offset, val);
		break;
	case 2:
		bus_space_write_2(t, h, offset, htole16(val));
		break;
	case 4:
		bus_space_write_4(t, h, offset, htole32(val));
		break;
	default:
		return;
	}
}
Exemple #29
0
static int
amdpm_smbus_read_1(struct amdpm_softc *sc, uint8_t cmd, i2c_op_t op)
{
	uint16_t data = 0;
	uint8_t ret;
	int off = (sc->sc_nforce ? 0xe0 : 0);

	/* first clear gsr */
	amdpm_smbus_clear_gsr(sc);  

	/* write smbus slave address to register */
	data = sc->sc_smbus_slaveaddr;
	data <<= 1;
	data |= AMDPM_8111_SMBUS_READ;    
	bus_space_write_1(sc->sc_iot, sc->sc_ioh,
	    AMDPM_8111_SMBUS_HOSTADDR - off, data);
	
	/* store cmd */
	bus_space_write_1(sc->sc_iot, sc->sc_ioh,
	    AMDPM_8111_SMBUS_HOSTCMD - off, cmd);
	/* host start */
	bus_space_write_2(sc->sc_iot, sc->sc_ioh,
	    AMDPM_8111_SMBUS_CTRL - off, AMDPM_8111_SMBUS_GSR_RB);
	
	/* check for errors */
	if (amdpm_smbus_check_done(sc, op) < 0)
		return -1;
	
	/* store data */    
	data = bus_space_read_2(sc->sc_iot, sc->sc_ioh,
	    AMDPM_8111_SMBUS_HOSTDATA - off);
	ret = (uint8_t)(data & 0x00FF);
	return ret;
}
Exemple #30
0
void
ofw_pci_write_config_common(device_t dev, u_int regmax, u_long offset,
                            u_int bus, u_int slot, u_int func, u_int reg, uint32_t val, int width)
{
    struct ofw_pci_softc *sc;
    bus_space_handle_t bh;

    sc = device_get_softc(dev);
    if (bus < sc->sc_pci_secbus || bus > sc->sc_pci_subbus ||
            slot > PCI_SLOTMAX || func > PCI_FUNCMAX || reg > regmax)
        return;

    bh = sc->sc_pci_bh[OFW_PCI_CS_CONFIG];
    switch (width) {
    case 1:
        bus_space_write_1(sc->sc_pci_cfgt, bh, offset, val);
        break;
    case 2:
        bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
        break;
    case 4:
        bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
        break;
    default:
        panic("%s: bad width %d", __func__, width);
        /* NOTREACHED */
    }
}