static inline void
cpsw_set_rxdesc(struct cpsw_softc * const sc, const u_int i,
struct cpsw_cpdma_bd * const bdp)
{
const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i;
bus_space_write_region_4(sc->sc_bst, sc->sc_bsh_rxdescs, o,
(uint32_t *)bdp, 4);
}
static int
cfi_0002_program_page(device_t self, flash_off_t offset, const uint8_t *datap)
{
struct nor_softc * const sc = device_private(self);
KASSERT(sc != NULL);
KASSERT(sc->sc_nor_if != NULL);
struct cfi *cfi = (struct cfi * const)sc->sc_nor_if->private;
KASSERT(cfi != NULL);
struct nor_chip * const chip = &sc->sc_chip;
KASSERT(chip != NULL);
KASSERT(chip->nc_page_mask != 0);
KASSERT((offset & ~chip->nc_page_mask) == 0);
KASSERT (chip->nc_page_size != 0);
KASSERT((chip->nc_page_size & ((1 << cfi->cfi_portwidth) - 1)) == 0);
CFI_0002_STATS_INC(cfi, program_page);
bus_size_t count = chip->nc_page_size >> cfi->cfi_portwidth;
/* #words/page */
bus_size_t sa = offset << (3 - cfi->cfi_portwidth);
/* sector addr */
uint32_t wc = count - 1; /* #words - 1 */
int error = cfi_0002_busy_wait(cfi, offset, cfi_0002_time_dflt(cfi));
if (error != 0)
return ETIMEDOUT;
cfi_cmd(cfi, cfi->cfi_unlock_addr1, 0xaa);
cfi_cmd(cfi, cfi->cfi_unlock_addr2, 0x55);
cfi_cmd(cfi, sa, 0x25); /* Write To Buffer */
cfi_cmd(cfi, sa, wc);
switch(cfi->cfi_portwidth) {
case 0:
bus_space_write_region_1(cfi->cfi_bst, cfi->cfi_bsh, offset,
(const uint8_t *)datap, count);
break;
case 1:
bus_space_write_region_2(cfi->cfi_bst, cfi->cfi_bsh, offset,
(const uint16_t *)datap, count);
break;
case 2:
bus_space_write_region_4(cfi->cfi_bst, cfi->cfi_bsh, offset,
(const uint32_t *)datap, count);
break;
default:
panic("%s: bad port width %d\n", __func__, cfi->cfi_portwidth);
};
cfi_cmd(cfi, sa, 0x29); /* Write Buffer Program Confirm */
error = cfi_0002_busy_wait(cfi, offset, cfi_0002_time_write_nbyte(cfi));
return error;
}
void
platform_mp_start_ap(void)
{
bus_space_handle_t scu, rst, ram;
int reg;
if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE,
SCU_SIZE, 0, &scu) != 0)
panic("Couldn't map the SCU\n");
if (bus_space_map(fdtbus_bs_tag, RSTMGR_PHYSBASE,
RSTMGR_SIZE, 0, &rst) != 0)
panic("Couldn't map the reset manager (RSTMGR)\n");
if (bus_space_map(fdtbus_bs_tag, RAM_PHYSBASE,
RAM_SIZE, 0, &ram) != 0)
panic("Couldn't map the first physram page\n");
/* Invalidate SCU cache tags */
bus_space_write_4(fdtbus_bs_tag, scu,
SCU_INV_TAGS_REG, 0x0000ffff);
/*
* Erratum ARM/MP: 764369 (problems with cache maintenance).
* Setting the "disable-migratory bit" in the undocumented SCU
* Diagnostic Control Register helps work around the problem.
*/
reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL);
reg |= (SCU_DIAG_DISABLE_MIGBIT);
bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, reg);
/* Put CPU1 to reset state */
bus_space_write_4(fdtbus_bs_tag, rst, MPUMODRST, MPUMODRST_CPU1);
/* Enable the SCU, then clean the cache on this core */
reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
reg |= (SCU_CONTROL_ENABLE);
bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG, reg);
/* Set up trampoline code */
mpentry_addr = (char *)pmap_kextract((vm_offset_t)mpentry);
bus_space_write_region_4(fdtbus_bs_tag, ram, 0,
(uint32_t *)&socfpga_trampoline, 8);
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
/* Put CPU1 out from reset */
bus_space_write_4(fdtbus_bs_tag, rst, MPUMODRST, 0);
armv7_sev();
bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
bus_space_unmap(fdtbus_bs_tag, rst, RSTMGR_SIZE);
bus_space_unmap(fdtbus_bs_tag, ram, RAM_SIZE);
}
static inline void
cpsw_set_rxdesc(struct cpsw_softc * const sc, const u_int i,
struct cpsw_cpdma_bd * const bdp)
{
const bus_size_t o = sizeof(struct cpsw_cpdma_bd) * i;
uint32_t * const dp = bdp->word;
const bus_size_t c = __arraycount(bdp->word);
KERNHIST_FUNC(__func__);
KERNHIST_CALLED_5(cpswhist, sc, i, bdp, 0);
KERNHIST_LOG(cpswhist, "%08x %08x %08x %08x\n",
dp[0], dp[1], dp[2], dp[3]);
bus_space_write_region_4(sc->sc_bst, sc->sc_bsh_rxdescs, o, dp, c);
}
void
platform_mp_start_ap(void)
{
bus_space_handle_t scu;
bus_space_handle_t imem;
bus_space_handle_t pmu;
uint32_t val;
int i;
if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE, SCU_SIZE, 0, &scu) != 0)
panic("Could not map the SCU");
if (bus_space_map(fdtbus_bs_tag, IMEM_PHYSBASE,
IMEM_SIZE, 0, &imem) != 0)
panic("Could not map the IMEM");
if (bus_space_map(fdtbus_bs_tag, PMU_PHYSBASE, PMU_SIZE, 0, &pmu) != 0)
panic("Could not map the PMU");
/*
* Invalidate SCU cache tags. The 0x0000ffff constant invalidates all
* ways on all cores 0-3. Per the ARM docs, it's harmless to write to
* the bits for cores that are not present.
*/
bus_space_write_4(fdtbus_bs_tag, scu, SCU_INV_TAGS_REG, 0x0000ffff);
/* Make sure all cores except the first are off */
val = bus_space_read_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON);
for (i = 1; i < mp_ncpus; i++)
val |= 1 << i;
bus_space_write_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON, val);
/* Enable SCU power domain */
val = bus_space_read_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON);
val &= ~PMU_PWRDN_SCU;
bus_space_write_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON, val);
/* Enable SCU */
val = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG,
val | SCU_CONTROL_ENABLE);
/*
* Cores will execute the code which resides at the start of
* the on-chip bootram/sram after power-on. This sram region
* should be reserved and the trampoline code that directs
* the core to the real startup code in ram should be copied
* into this sram region.
*
* First set boot function for the sram code.
*/
mpentry_addr = (char *)pmap_kextract((vm_offset_t)mpentry);
/* Copy trampoline to sram, that runs during startup of the core */
bus_space_write_region_4(fdtbus_bs_tag, imem, 0,
(uint32_t *)&rk30xx_boot2, 8);
cpu_idcache_wbinv_all();
cpu_l2cache_wbinv_all();
/* Start all cores */
val = bus_space_read_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON);
for (i = 1; i < mp_ncpus; i++)
val &= ~(1 << i);
bus_space_write_4(fdtbus_bs_tag, pmu, PMU_PWRDN_CON, val);
armv7_sev();
bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
bus_space_unmap(fdtbus_bs_tag, imem, IMEM_SIZE);
bus_space_unmap(fdtbus_bs_tag, pmu, PMU_SIZE);
}
void
bs_through_bs_wr_4(bus_space_tag_t t, bus_space_handle_t bsh,
bus_size_t offset, const u_int32_t *addr, bus_size_t count)
{
bus_space_write_region_4(t->bs_base, bsh, offset, addr, count);
}
