static void do_setup_dpll(u32 const base, const struct dpll_params *params,
u8 lock, char *dpll)
{
u32 temp, M, N;
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
if (!params)
return;
temp = readl(&dpll_regs->cm_clksel_dpll);
if (check_for_lock(base)) {
/*
* The Dpll has already been locked by rom code using CH.
* Check if M,N are matching with Ideal nominal opp values.
* If matches, skip the rest otherwise relock.
*/
M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
if ((M != (params->m)) || (N != (params->n))) {
debug("\n %s Dpll locked, but not for ideal M = %d,"
"N = %d values, current values are M = %d,"
"N= %d" , dpll, params->m, params->n,
M, N);
} else {
/* Dpll locked with ideal values for nominal opps. */
debug("\n %s Dpll already locked with ideal"
"nominal opp values", dpll);
bypass_dpll(base);
goto setup_post_dividers;
}
}
bypass_dpll(base);
/* Set M & N */
temp &= ~CM_CLKSEL_DPLL_M_MASK;
temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
temp &= ~CM_CLKSEL_DPLL_N_MASK;
temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
writel(temp, &dpll_regs->cm_clksel_dpll);
setup_post_dividers:
setup_post_dividers(base, params);
/* Lock */
if (lock)
do_lock_dpll(base);
/* Wait till the DPLL locks */
if (lock)
wait_for_lock(base);
}
/*
* Lock MPU dpll
*
* Resulting MPU frequencies:
* 4430 ES1.0 : 600 MHz
* 4430 ES2.x : 792 MHz (OPP Turbo)
* 4460 : 920 MHz (OPP Turbo) - DCC disabled
*/
void configure_mpu_dpll(void)
{
const struct dpll_params *params;
struct dpll_regs *mpu_dpll_regs;
u32 omap_rev;
omap_rev = omap_revision();
/*
* DCC and clock divider settings for 4460.
* DCC is required, if more than a certain frequency is required.
* For, 4460 > 1GHZ.
* 5430 > 1.4GHZ.
*/
if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
mpu_dpll_regs =
(struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
CM_CLKSEL_DCC_EN_MASK);
}
params = get_mpu_dpll_params(*dplls_data);
do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
debug("MPU DPLL locked\n");
}
/*
* Lock MPU dpll
*
* Resulting MPU frequencies:
* 4430 ES1.0 : 600 MHz
* 4430 ES2.x : 792 MHz (OPP Turbo)
* 4460 : 920 MHz (OPP Turbo) - DCC disabled
*/
void configure_mpu_dpll(void)
{
const struct dpll_params *params;
struct dpll_regs *mpu_dpll_regs;
u32 omap4_rev, sysclk_ind;
omap4_rev = omap_revision();
sysclk_ind = get_sys_clk_index();
if (omap4_rev == OMAP4430_ES1_0)
params = &mpu_dpll_params_1200mhz[sysclk_ind];
else if (omap4_rev < OMAP4460_ES1_0)
params = &mpu_dpll_params_1584mhz[sysclk_ind];
else
params = &mpu_dpll_params_1840mhz[sysclk_ind];
/* DCC and clock divider settings for 4460 */
if (omap4_rev >= OMAP4460_ES1_0) {
mpu_dpll_regs =
(struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu;
bypass_dpll(&prcm->cm_clkmode_dpll_mpu);
clrbits_le32(&prcm->cm_mpu_mpu_clkctrl,
MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
CM_CLKSEL_DCC_EN_MASK);
}
do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK);
debug("MPU DPLL locked\n");
}
void do_setup_dpll(const struct dpll_regs *dpll_regs,
const struct dpll_params *params)
{
u32 temp;
if (!params)
return;
temp = readl(dpll_regs->cm_clksel_dpll);
bypass_dpll(dpll_regs);
/* Set M & N */
temp &= ~CM_CLKSEL_DPLL_M_MASK;
temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
temp &= ~CM_CLKSEL_DPLL_N_MASK;
temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
writel(temp, dpll_regs->cm_clksel_dpll);
setup_post_dividers(dpll_regs, params);
/* Wait till the DPLL locks */
do_lock_dpll(dpll_regs);
wait_for_lock(dpll_regs);
}
static void do_setup_dpll(u32 *const base, const struct dpll_params *params,
u8 lock)
{
u32 temp;
struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
bypass_dpll(base);
/* Set M & N */
temp = readl(&dpll_regs->cm_clksel_dpll);
temp &= ~CM_CLKSEL_DPLL_M_MASK;
temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
temp &= ~CM_CLKSEL_DPLL_N_MASK;
temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
writel(temp, &dpll_regs->cm_clksel_dpll);
/* Lock */
if (lock)
do_lock_dpll(base);
/* Setup post-dividers */
if (params->m2 >= 0)
writel(params->m2, &dpll_regs->cm_div_m2_dpll);
if (params->m3 >= 0)
writel(params->m3, &dpll_regs->cm_div_m3_dpll);
if (params->m4 >= 0)
writel(params->m4, &dpll_regs->cm_div_m4_dpll);
if (params->m5 >= 0)
writel(params->m5, &dpll_regs->cm_div_m5_dpll);
if (params->m6 >= 0)
writel(params->m6, &dpll_regs->cm_div_m6_dpll);
if (params->m7 >= 0)
writel(params->m7, &dpll_regs->cm_div_m7_dpll);
/* Wait till the DPLL locks */
if (lock)
wait_for_lock(base);
}
