void on_cas_init(void)
{
u32 cas_id = 0;
cas_adapter_cfg_t cas_cfg = {0};
cas_module_cfg_t cas_module_cfg = {0};
p_ca_buffer = mtos_malloc(CA_DATA_SIZE);
MT_ASSERT(NULL != p_ca_buffer);
memset(p_ca_buffer, 0, CA_DATA_SIZE);
//config cas adapter
cas_cfg.p_smc_drv[0] = dev_find_identifier(NULL, DEV_IDT_TYPE, SYS_DEV_TYPE_SMC);
cas_cfg.slot_num = 1;
cas_cfg.p_task_stack = mtos_malloc(4096);
MT_ASSERT(NULL != cas_cfg.p_task_stack);
cas_cfg.stack_size = 4096;
cas_cfg.task_prio = DRV_CAS_ADAPTER_TASK_PRIORITY;
cas_cfg.p_data_task_stack = mtos_malloc(4096);
MT_ASSERT(NULL != cas_cfg.p_data_task_stack);
cas_cfg.data_stack_size = 4096;
//cas_cfg.data_task_prio = MDL_CAS_TASK_PRIO_BEGIN+1;
#ifndef WIN32
cas_init(&cas_cfg);
#endif
cas_module_cfg.cas_lib_type = CAS_LIB_TEST;
cas_module_cfg.p_dmx_dev = dev_find_identifier(NULL, DEV_IDT_TYPE, SYS_DEV_TYPE_PTI);
cas_module_cfg.max_mail_num = 30;
cas_module_cfg.mail_policy = POLICY_BY_ID;
cas_module_cfg.flash_start_adr = dm_get_block_addr(class_get_handle_by_id(DM_CLASS_ID), CADATA_BLOCK_ID)
- get_flash_addr();
OS_PRINTF("set ca addr is 0x%x\n", cas_module_cfg.flash_start_adr);
cas_module_cfg.flash_size = CA_DATA_SIZE;
cas_module_cfg.level = 0;
cas_module_cfg.task_prio = MDL_CAS_TASK_PRIO_BEGIN;
cas_module_cfg.end_task_prio = MDL_CAS_TASK_PRIO_END;
cas_module_cfg.stack_size = 8 * KBYTES;
cas_module_cfg.p_task_stack = mtos_malloc(8 * KBYTES);
cas_module_cfg.filter_mode = ECM_FILTER_CONTINUOUS_DISABLED;
cas_module_cfg.nvram_read = nvram_read;
cas_module_cfg.nvram_write = nvram_write;
cas_module_cfg.queue_task_prio = LOWEST_TASK_PRIORITY -2; //LOWEST_TASK_PRIORITY -1; //panhui
MT_ASSERT(cas_module_cfg.p_task_stack != NULL);
#ifndef WIN32
cas_tr_attach(&cas_module_cfg, &cas_id);
cas_module_init(CAS_ID_TR);
#endif
register_monitor_table();
}
void
cas_watchdog(struct ifnet *ifp)
{
struct cas_softc *sc = ifp->if_softc;
DPRINTF(sc, ("cas_watchdog: CAS_RX_CONFIG %x CAS_MAC_RX_STATUS %x "
"CAS_MAC_RX_CONFIG %x\n",
bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_RX_CONFIG),
bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_STATUS),
bus_space_read_4(sc->sc_memt, sc->sc_memh, CAS_MAC_RX_CONFIG)));
log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
++ifp->if_oerrors;
/* Try to get more packets going. */
cas_init(ifp);
}
void on_cas_init(void)
{
u32 cas_id = 0;
cas_adapter_cfg_t cas_cfg = {0};
cas_module_cfg_t cas_module_cfg = {0};
p_ca_buffer = mtos_malloc(CA_DATA_SIZE);
MT_ASSERT(NULL != p_ca_buffer);
memset(p_ca_buffer, 0, CA_DATA_SIZE);
//config cas adapter
cas_cfg.p_smc_drv[0] = dev_find_identifier(NULL, DEV_IDT_TYPE, SYS_DEV_TYPE_SMC);
cas_cfg.slot_num = 1;
#if 1
cas_cfg.p_task_stack = mtos_malloc(4096);
cas_cfg.stack_size = 4096;
cas_cfg.task_prio = DRV_CAS_ADAPTER_TASK_PRIORITY;
#ifndef WIN32
cas_init(&cas_cfg);
cas_module_cfg.p_dmx_dev = dev_find_identifier(NULL, DEV_IDT_TYPE, SYS_DEV_TYPE_PTI);
cas_module_cfg.nvram_read = nvram_read;
cas_module_cfg.nvram_write = nvram_write;
cas_module_cfg.flash_start_adr = dm_get_block_addr(class_get_handle_by_id(DM_CLASS_ID), CADATA_BLOCK_ID)
- get_flash_addr();
OS_PRINTF("set ca addr is 0x%x\n", cas_module_cfg.flash_start_adr);
cas_module_cfg.flash_size = CA_DATA_SIZE;
cas_module_cfg.task_prio = DRV_CAS_MODUL_TASK_PRIORITY_START;
cas_module_cfg.end_task_prio = DRV_CAS_MODUL_TASK_PRIORITY_END;
cas_module_cfg.queue_task_prio = CUSTOMER_TASK_PRIORITY;
OS_PRINTF("####debug cas_tr_attach 0\n");
cas_tr_attach(&cas_module_cfg, &cas_id);
OS_PRINTF("####debug cas_tr_attach\n");
cas_module_init(AP_CAS_ID);
OS_PRINTF("####debug cas_module_init\n");
#endif
#endif
register_monitor_table();
}
void on_cas_init(void)
{
u32 cas_id = 0;
cas_adapter_cfg_t cas_cfg = {0};
cas_module_cfg_t cas_module_cfg = {0};
p_ca_buffer = mtos_malloc(CA_DATA_SIZE);
MT_ASSERT(NULL != p_ca_buffer);
memset(p_ca_buffer, 0, CA_DATA_SIZE);
//config cas adapter
cas_cfg.p_smc_drv[0] = dev_find_identifier(NULL, DEV_IDT_TYPE, SYS_DEV_TYPE_SMC);
cas_cfg.slot_num = 1;
cas_cfg.p_task_stack = mtos_malloc(4096);
cas_cfg.stack_size = 4096;
cas_cfg.task_prio = DRV_CAS_ADAPTER_TASK_PRIORITY;
#ifndef WIN32
cas_init(&cas_cfg);
#endif
cas_module_cfg.p_dmx_dev = dev_find_identifier(NULL, DEV_IDT_TYPE, SYS_DEV_TYPE_PTI);
cas_module_cfg.nvram_read = NULL;
cas_module_cfg.nvram_write = NULL;
cas_module_cfg.flash_start_adr = dm_get_block_addr(class_get_handle_by_id(DM_CLASS_ID), CADATA_BLOCK_ID)
- get_flash_addr();
OS_PRINTF("set ca addr is 0x%x\n", cas_module_cfg.flash_start_adr);
cas_module_cfg.flash_size = CA_DATA_SIZE;
cas_module_cfg.task_prio = MDL_CAS_TASK_PRIO_BEGIN; //need fixed
cas_module_cfg.end_task_prio = MDL_CAS_TASK_PRIO_END; //need fixed
cas_module_cfg.machine_serial_get = NULL;
cas_module_cfg.query_check = force_channel_pg_check;
#ifndef WIN32
cas_ds_attach_v5(&cas_module_cfg, &cas_id);
cas_module_init(CAS_ID_DS);
#endif
register_monitor_table();
}
/*
* Process an ioctl request.
*/
int
cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
{
struct cas_softc *sc = ifp->if_softc;
struct ifaddr *ifa = (struct ifaddr *)data;
struct ifreq *ifr = (struct ifreq *)data;
int s, error = 0;
s = splnet();
if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) {
splx(s);
return (error);
}
switch (cmd) {
case SIOCSIFADDR:
ifp->if_flags |= IFF_UP;
if ((ifp->if_flags & IFF_RUNNING) == 0)
cas_init(ifp);
#ifdef INET
if (ifa->ifa_addr->sa_family == AF_INET)
arp_ifinit(&sc->sc_arpcom, ifa);
#endif
break;
case SIOCSIFFLAGS:
if (ifp->if_flags & IFF_UP) {
if ((ifp->if_flags & IFF_RUNNING) &&
((ifp->if_flags ^ sc->sc_if_flags) &
(IFF_ALLMULTI | IFF_PROMISC)) != 0)
cas_setladrf(sc);
else {
if ((ifp->if_flags & IFF_RUNNING) == 0)
cas_init(ifp);
}
} else {
if (ifp->if_flags & IFF_RUNNING)
cas_stop(ifp, 1);
}
sc->sc_if_flags = ifp->if_flags;
#ifdef CAS_DEBUG
sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0;
#endif
break;
case SIOCSIFMTU:
if (ifr->ifr_mtu > ETHERMTU || ifr->ifr_mtu < ETHERMIN) {
error = EINVAL;
} else if (ifp->if_mtu != ifr->ifr_mtu) {
ifp->if_mtu = ifr->ifr_mtu;
}
break;
case SIOCADDMULTI:
case SIOCDELMULTI:
error = (cmd == SIOCADDMULTI) ?
ether_addmulti(ifr, &sc->sc_arpcom) :
ether_delmulti(ifr, &sc->sc_arpcom);
if (error == ENETRESET) {
/*
* Multicast list has changed; set the hardware filter
* accordingly.
*/
if (ifp->if_flags & IFF_RUNNING)
cas_setladrf(sc);
error = 0;
}
break;
case SIOCGIFMEDIA:
case SIOCSIFMEDIA:
error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
break;
default:
error = ENOTTY;
break;
}
splx(s);
return (error);
}
int
cas_intr(void *v)
{
struct cas_softc *sc = (struct cas_softc *)v;
struct ifnet *ifp = &sc->sc_arpcom.ac_if;
bus_space_tag_t t = sc->sc_memt;
bus_space_handle_t seb = sc->sc_memh;
u_int32_t status;
int r = 0;
status = bus_space_read_4(t, seb, CAS_STATUS);
DPRINTF(sc, ("%s: cas_intr: cplt %xstatus %b\n",
sc->sc_dev.dv_xname, (status>>19), status, CAS_INTR_BITS));
if ((status & CAS_INTR_PCS) != 0)
r |= cas_pint(sc);
if ((status & (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR |
CAS_INTR_RX_COMP_FULL | CAS_INTR_BERR)) != 0)
r |= cas_eint(sc, status);
if ((status & (CAS_INTR_TX_EMPTY | CAS_INTR_TX_INTME)) != 0)
r |= cas_tint(sc, status);
if ((status & (CAS_INTR_RX_DONE | CAS_INTR_RX_NOBUF)) != 0)
r |= cas_rint(sc);
/* We should eventually do more than just print out error stats. */
if (status & CAS_INTR_TX_MAC) {
int txstat = bus_space_read_4(t, seb, CAS_MAC_TX_STATUS);
#ifdef CAS_DEBUG
if (txstat & ~CAS_MAC_TX_XMIT_DONE)
printf("%s: MAC tx fault, status %x\n",
sc->sc_dev.dv_xname, txstat);
#endif
if (txstat & (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_PKT_TOO_LONG))
cas_init(ifp);
}
if (status & CAS_INTR_RX_MAC) {
int rxstat = bus_space_read_4(t, seb, CAS_MAC_RX_STATUS);
#ifdef CAS_DEBUG
if (rxstat & ~CAS_MAC_RX_DONE)
printf("%s: MAC rx fault, status %x\n",
sc->sc_dev.dv_xname, rxstat);
#endif
/*
* On some chip revisions CAS_MAC_RX_OVERFLOW happen often
* due to a silicon bug so handle them silently.
*/
if (rxstat & CAS_MAC_RX_OVERFLOW) {
ifp->if_ierrors++;
cas_init(ifp);
}
#ifdef CAS_DEBUG
else if (rxstat & ~(CAS_MAC_RX_DONE | CAS_MAC_RX_FRAME_CNT))
printf("%s: MAC rx fault, status %x\n",
sc->sc_dev.dv_xname, rxstat);
#endif
}
return (r);
}
void Orb_thread_support_init(void) {
/*init order is sensitive!*/
cas_init();
tls_init();
cel_init();
}
