void main(void)
{
struct mem_timings *mem;
void *entry;
int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP);
/* Clock must be initialized before console_init, otherwise you may need
* to re-initialize serial console drivers again. */
mem = setup_clock();
console_init();
setup_power(is_resume);
setup_memory(mem, is_resume);
if (is_resume) {
wakeup();
}
setup_storage();
setup_gpio();
setup_graphics();
/* Set SPI (primary CBFS media) clock to 50MHz and configure pinmux. */
exynos_pinmux_spi1();
clock_set_rate(PERIPH_ID_SPI1, 50000000);
cbmem_initialize_empty();
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
stage_exit(entry);
}
void romstage_init(void)
{
void *entry;
#if CONFIG_COLLECT_TIMESTAMPS
uint64_t start_romstage_time;
uint64_t before_dram_time;
uint64_t after_dram_time;
uint64_t base_time = timestamp_get();
start_romstage_time = timestamp_get();
#endif
rkclk_set_pll();
console_init();
#if CONFIG_COLLECT_TIMESTAMPS
before_dram_time = timestamp_get();
#endif
dram_main();
#if CONFIG_COLLECT_TIMESTAMPS
after_dram_time = timestamp_get();
#endif
udelay(100);
cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_init(base_time);
timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
timestamp_add(TS_AFTER_INITRAM, after_dram_time );
#endif
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_add_now(TS_END_ROMSTAGE);
#endif
stage_exit(entry);
}
void main(void)
{
extern struct mem_timings mem_timings;
void *entry;
int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP);
/* Clock must be initialized before console_init, otherwise you may need
* to re-initialize serial console drivers again. */
system_clock_init();
console_init();
setup_power(is_resume);
setup_memory(&mem_timings, is_resume);
primitive_mem_test();
if (is_resume) {
wakeup();
}
setup_storage();
setup_gpio();
setup_ec();
simple_spi_test();
/* Set SPI (primary CBFS media) clock to 50MHz. */
/* if this is uncommented SPI will not work correctly. */
clock_set_rate(PERIPH_ID_SPI1, 50000000);
simple_spi_test();
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
simple_spi_test();
stage_exit(entry);
}
static void *cbfs_load_ramstage(uint32_t cbmem_id, const char *name,
const struct cbmem_entry **cbmem_entry)
{
void *entry;
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, name);
if ((void *)entry == (void *) -1)
entry = NULL;
return entry;
}
void main(void)
{
struct mem_timings *mem;
struct arm_clk_ratios *arm_ratios;
int ret;
void *entry;
clock_set_rate(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
/* Clock must be initialized before console_init, otherwise you may need
* to re-initialize serial console drivers again. */
mem = get_mem_timings();
arm_ratios = get_arm_clk_ratios();
system_clock_init(mem, arm_ratios);
console_init();
/*
* FIXME: Do necessary I2C init so low-level PMIC code doesn't need to.
* Also, we should only call power_init() on cold boot.
*/
power_init();
if (!mem) {
printk(BIOS_CRIT, "Unable to auto-detect memory timings\n");
while(1);
}
printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n",
mem->mem_manuf,
mem->mem_type,
mem->mpll_mdiv,
mem->frequency_mhz);
ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE);
if (ret) {
printk(BIOS_ERR, "Memory controller init failed, err: %x\n",
ret);
while(1);
}
/* Set up MMU and caches */
mmu_setup_by_mva(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB);
initialize_s5p_mshc();
graphics();
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);
stage_exit(entry);
}
static void cbfs_and_run_core(const char *filename, unsigned ebp)
{
u8 *dst;
print_debug("Loading image.\n");
dst = cbfs_load_stage(filename);
if ((void *)dst == (void *) -1)
die("FATAL: Essential component is missing.\n");
print_debug("Jumping to image.\n");
__asm__ volatile (
"movl %%eax, %%ebp\n"
"jmp *%%edi\n"
:: "a"(ebp), "D"(dst)
);
}
void main(void)
{
const char *stage_name = "fallback/romstage";
void *entry;
bootblock_cpu_init();
bootblock_mainboard_init();
if (CONFIG_BOOTBLOCK_CONSOLE) {
console_init();
exception_init();
}
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name);
if (entry) stage_exit(entry);
hlt();
}
void main(void)
{
const char *stage_name = "fallback/romstage";
void *entry;
if (boot_cpu()) {
bootblock_cpu_init();
bootblock_mainboard_init();
}
console_init();
printk(BIOS_INFO, "hello from bootblock\n");
printk(BIOS_INFO, "bootblock main(): loading romstage\n");
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name);
printk(BIOS_INFO, "bootblock main(): jumping to romstage\n");
if (entry) stage_exit(entry);
hlt();
}
void main(void)
{
void *entry;
clock_early_uart();
// Serial out, tristate off.
pinmux_set_config(PINMUX_KB_ROW9_INDEX, PINMUX_KB_ROW9_FUNC_UA3);
// Serial in, tristate_on.
pinmux_set_config(PINMUX_KB_ROW10_INDEX, PINMUX_KB_ROW10_FUNC_UA3 |
PINMUX_TRISTATE |
PINMUX_INPUT_ENABLE);
if (CONFIG_BOOTBLOCK_CONSOLE)
console_init();
clock_init();
bootblock_mainboard_init();
pinmux_set_config(PINMUX_CORE_PWR_REQ_INDEX,
PINMUX_CORE_PWR_REQ_FUNC_PWRON);
pinmux_set_config(PINMUX_CPU_PWR_REQ_INDEX,
PINMUX_CPU_PWR_REQ_FUNC_CPU);
pinmux_set_config(PINMUX_PWR_INT_N_INDEX,
PINMUX_PWR_INT_N_FUNC_PMICINTR |
PINMUX_TRISTATE |
PINMUX_INPUT_ENABLE);
power_enable_cpu_rail();
power_ungate_cpu();
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage");
if (entry)
clock_cpu0_config_and_reset(entry);
hlt();
}
void main(void)
{
const char *stage_name = "fallback/romstage";
void *entry;
uint32_t sctlr;
/* Globally disable MMU, caches, and branch prediction (these should
* be disabled by default on reset) */
sctlr = read_sctlr();
sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I);
write_sctlr(sctlr);
armv7_invalidate_caches();
/*
* Re-enable caches and branch prediction. MMU will be set up later.
* Note: If booting from USB, we need to disable branch prediction
* before copying from USB into RAM (FIXME: why?)
*/
sctlr = read_sctlr();
sctlr |= SCTLR_C | SCTLR_Z | SCTLR_I;
write_sctlr(sctlr);
if (boot_cpu()) {
bootblock_cpu_init();
bootblock_mainboard_init();
}
console_init();
printk(BIOS_INFO, "hello from bootblock\n");
printk(BIOS_INFO, "bootblock main(): loading romstage\n");
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name);
printk(BIOS_INFO, "bootblock main(): jumping to romstage\n");
if (entry) stage_exit(entry);
hlt();
}
