void reset_md1_md3_pccif(struct ccci_modem *md)
{
unsigned int tx_channel = 0;
int i;
struct md_ccif_ctrl *md_ctrl = (struct md_ccif_ctrl *)md->private_data;
struct md_hw_info *hw_info = md_ctrl->hw_info;
/* clear occupied channel */
while (tx_channel < 16) {
if (ccif_read32(hw_info->md1_pccif_base, PCCIF_BUSY) & (1<<tx_channel))
ccif_write32(hw_info->md1_pccif_base, PCCIF_TCHNUM, tx_channel);
if (ccif_read32(hw_info->md3_pccif_base, PCCIF_BUSY) & (1<<tx_channel))
ccif_write32(hw_info->md3_pccif_base, PCCIF_TCHNUM, tx_channel);
tx_channel++;
}
/* clear un-ached channel *.
ccif_write32(hw_info->md1_pccif_base, PCCIF_ACK, ccif_read32(hw_info->md3_pccif_base, PCCIF_BUSY));
ccif_write32(hw_info->md3_pccif_base, PCCIF_ACK, ccif_read32(hw_info->md1_pccif_base, PCCIF_BUSY));
/* clear SRAM */
for (i = 0; i < PCCIF_SRAM_SIZE/sizeof(unsigned int); i++) {
ccif_write32(hw_info->md1_pccif_base, PCCIF_CHDATA + i*sizeof(unsigned int), 0);
ccif_write32(hw_info->md3_pccif_base, PCCIF_CHDATA + i*sizeof(unsigned int), 0);
}
pr_debug("[C2K] Dump MD1 PCCIF\n");
ccci_mem_dump(-1, hw_info->md1_pccif_base, 0x300);
pr_debug("[C2K] Dump MD3 PCCIF\n");
ccci_mem_dump(-1, hw_info->md3_pccif_base, 0x300);
}
int md_ccif_let_md_go(struct ccci_modem *md)
{
struct md_ccif_ctrl *md_ctrl = (struct md_ccif_ctrl *)md->private_data;
if(MD_IN_DEBUG(md))
{
CCCI_INF_MSG(md->index, TAG, "DBG_FLAG_JTAG is set\n");
return -1;
}
CCCI_INF_MSG(md->index, TAG, "md_ccif_let_md_go\n");
// set the start address to let modem to run
ccif_write32(md_ctrl->md_boot_slave_Key, 0, MD2_BOOT_VECTOR_KEY_VALUE); // make boot vector programmable
ccif_write32(md_ctrl->md_boot_slave_Vector, 0, MD2_BOOT_VECTOR_VALUE); // after remap, MD ROM address is 0 from MD's view
ccif_write32(md_ctrl->md_boot_slave_En, 0, MD2_BOOT_VECTOR_EN_VALUE); // make boot vector take effect
return 0;
}
int md_ccif_power_on(struct ccci_modem *md)
{
int ret = 0;
struct md_ccif_ctrl *md_ctrl = (struct md_ccif_ctrl *)md->private_data;
switch(md->index)
{
case MD_SYS2:
ret = md_power_on(SYS_MD2);
break;
}
CCCI_INF_MSG(md->index, TAG, "md_ccif_power_on:ret=%d\n",ret);
if(ret==0){
// disable MD WDT
ccif_write32(md_ctrl->md_rgu_base, WDT_MD_MODE, WDT_MD_MODE_KEY);
}
return ret;
}
int md_ccif_power_on(struct ccci_modem *md)
{
int ret = 0;
struct md_ccif_ctrl *md_ctrl = (struct md_ccif_ctrl *)md->private_data;
switch (md->index) {
case MD_SYS2:
#if defined(CONFIG_MTK_LEGACY)
CCCI_INF_MSG(md->index, TAG, "Call start md_power_on()\n");
ret = md_power_on(SYS_MD2);
CCCI_INF_MSG(md->index, TAG, "Call end md_power_on() ret=%d\n",
ret);
#else
CCCI_INF_MSG(md->index, TAG,
"Call start clk_prepare_enable()\n");
clk_prepare_enable(clk_scp_sys_md2_main);
CCCI_INF_MSG(md->index, TAG, "Call end clk_prepare_enable()\n");
#endif
break;
case MD_SYS3:
#if defined(CONFIG_MTK_LEGACY)
CCCI_INF_MSG(md->index, TAG, "Call start md_power_on()\n");
ret = md_power_on(SYS_MD2);
CCCI_INF_MSG(md->index, TAG, "Call end md_power_on() ret=%d\n",
ret);
#else
CCCI_INF_MSG(md->index, TAG,
"Call start clk_prepare_enable()\n");
clk_prepare_enable(clk_scp_sys_md3_main);
CCCI_INF_MSG(md->index, TAG, "Call end clk_prepare_enable()\n");
#endif
break;
}
CCCI_INF_MSG(md->index, TAG, "md_ccif_power_on:ret=%d\n", ret);
if (ret == 0 && md->index != MD_SYS3) {
/*disable MD WDT */
ccif_write32(md_ctrl->md_rgu_base, WDT_MD_MODE,
WDT_MD_MODE_KEY);
}
return ret;
}
/*need modify according to dummy ap*/
int md_ccif_let_md_go(struct ccci_modem *md)
{
struct md_ccif_ctrl *md_ctrl = (struct md_ccif_ctrl *)md->private_data;
if (MD_IN_DEBUG(md)) {
CCCI_INF_MSG(md->index, TAG, "DBG_FLAG_JTAG is set\n");
return -1;
}
CCCI_INF_MSG(md->index, TAG, "md_ccif_let_md_go\n");
switch (md->index) {
case MD_SYS2:
/*set the start address to let modem to run */
/*make boot vector programmable */
ccif_write32(md_ctrl->md_boot_slave_Key, 0, MD2_BOOT_VECTOR_KEY_VALUE);
/*after remap, MD ROM address is 0 from MD's view */
ccif_write32(md_ctrl->md_boot_slave_Vector, 0, MD2_BOOT_VECTOR_VALUE);
/*make boot vector take effect */
ccif_write32(md_ctrl->md_boot_slave_En, 0, MD2_BOOT_VECTOR_EN_VALUE);
break;
case MD_SYS3:
/*check if meta mode */
if (is_meta_mode() || get_boot_mode() == FACTORY_BOOT) {
ccif_write32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_CONFIG,
(ccif_read32
(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_CONFIG) | ETS_SEL_BIT));
}
/*step 1: set C2K boot mode */
ccif_write32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_CONFIG,
(ccif_read32
(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_CONFIG) & (~(0x7 << 8))) | (0x5 <<
8));
CCCI_INF_MSG(md->index, TAG, "C2K_CONFIG = 0x%x\n",
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_CONFIG));
/*step 2: config srcclkena selection mask */
ccif_write32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL,
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL) & (~(0x3 <<
4)));
ccif_write32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL,
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL) | (0x2 << 4));
CCCI_INF_MSG(md->index, TAG, "C2K_SPM_CTRL = 0x%x\n",
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL));
ccif_write32(md_ctrl->hw_info->sleep_base, SLEEP_CLK_CON,
ccif_read32(md_ctrl->hw_info->sleep_base,
SLEEP_CLK_CON) | 0xc);
ccif_write32(md_ctrl->hw_info->sleep_base, SLEEP_CLK_CON,
ccif_read32(md_ctrl->hw_info->sleep_base,
SLEEP_CLK_CON) & (~(0x1 << 14)));
ccif_write32(md_ctrl->hw_info->sleep_base, SLEEP_CLK_CON,
ccif_read32(md_ctrl->hw_info->sleep_base,
SLEEP_CLK_CON) | (0x1 << 12));
ccif_write32(md_ctrl->hw_info->sleep_base, SLEEP_CLK_CON,
ccif_read32(md_ctrl->hw_info->sleep_base,
SLEEP_CLK_CON) | (0x1 << 27));
CCCI_INF_MSG(md->index, TAG, "SLEEP_CLK_CON = 0x%x\n",
ccif_read32(md_ctrl->hw_info->sleep_base,
SLEEP_CLK_CON));
/*step 3: PMIC VTCXO_1 enable */
pmic_config_interface(0x0A02, 0xA12E, 0xFFFF, 0x0);
/*step 4: reset C2K */
#if 0
ccif_write32(md_ctrl->hw_info->toprgu_base,
TOP_RGU_WDT_SWSYSRST,
(ccif_read32
(md_ctrl->hw_info->toprgu_base,
TOP_RGU_WDT_SWSYSRST) | 0x88000000) & (~(0x1 <<
15)));
#else
mtk_wdt_set_c2k_sysrst(1);
#endif
CCCI_INF_MSG(md->index, TAG,
"[C2K] TOP_RGU_WDT_SWSYSRST = 0x%x\n",
ccif_read32(md_ctrl->hw_info->toprgu_base,
TOP_RGU_WDT_SWSYSRST));
/*step 5: mpu already set */
/*step 6: wake up C2K */
ccif_write32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL,
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL) | 0x1);
while (!
((ccif_read32
(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_STATUS) >> 1) & 0x1)) {
CCCI_INF_MSG(md->index, TAG,
"[C2K] C2K_STATUS = 0x%x\n",
ccif_read32(md_ctrl->hw_info->
infra_ao_base,
INFRA_AO_C2K_STATUS));
}
ccif_write32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL,
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL) & (~0x1));
CCCI_INF_MSG(md->index, TAG,
"[C2K] C2K_SPM_CTRL = 0x%x, C2K_STATUS = 0x%x\n",
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_SPM_CTRL),
ccif_read32(md_ctrl->hw_info->infra_ao_base,
INFRA_AO_C2K_STATUS));
break;
}
return 0;
}
