static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw); u32 n_mask = 0, k_mask = 0, m_mask = 0, p_mask = 0; struct _ccu_nkmp _nkmp; unsigned long flags; u32 reg; if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV) rate = rate * nkmp->fixed_post_div; _nkmp.min_n = nkmp->n.min ?: 1; _nkmp.max_n = nkmp->n.max ?: 1 << nkmp->n.width; _nkmp.min_k = nkmp->k.min ?: 1; _nkmp.max_k = nkmp->k.max ?: 1 << nkmp->k.width; _nkmp.min_m = 1; _nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width; _nkmp.min_p = 1; _nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1); ccu_nkmp_find_best(parent_rate, rate, &_nkmp); /* * If width is 0, GENMASK() macro may not generate expected mask (0) * as it falls under undefined behaviour by C standard due to shifts * which are equal or greater than width of left operand. This can * be easily avoided by explicitly checking if width is 0. */ if (nkmp->n.width) n_mask = GENMASK(nkmp->n.width + nkmp->n.shift - 1, nkmp->n.shift); if (nkmp->k.width) k_mask = GENMASK(nkmp->k.width + nkmp->k.shift - 1, nkmp->k.shift); if (nkmp->m.width) m_mask = GENMASK(nkmp->m.width + nkmp->m.shift - 1, nkmp->m.shift); if (nkmp->p.width) p_mask = GENMASK(nkmp->p.width + nkmp->p.shift - 1, nkmp->p.shift); spin_lock_irqsave(nkmp->common.lock, flags); reg = readl(nkmp->common.base + nkmp->common.reg); reg &= ~(n_mask | k_mask | m_mask | p_mask); reg |= ((_nkmp.n - nkmp->n.offset) << nkmp->n.shift) & n_mask; reg |= ((_nkmp.k - nkmp->k.offset) << nkmp->k.shift) & k_mask; reg |= ((_nkmp.m - nkmp->m.offset) << nkmp->m.shift) & m_mask; reg |= (ilog2(_nkmp.p) << nkmp->p.shift) & p_mask; writel(reg, nkmp->common.base + nkmp->common.reg); spin_unlock_irqrestore(nkmp->common.lock, flags); ccu_helper_wait_for_lock(&nkmp->common, nkmp->lock); return 0; }
static int ccu_nk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct ccu_nk *nk = hw_to_ccu_nk(hw); unsigned long flags; unsigned int n, k; u32 reg; if (nk->common.features & CCU_FEATURE_FIXED_POSTDIV) rate = rate * nk->fixed_post_div; ccu_nk_find_best(parent_rate, rate, 1 << nk->n.width, 1 << nk->k.width, &n, &k); spin_lock_irqsave(nk->common.lock, flags); reg = readl(nk->common.base + nk->common.reg); reg &= ~GENMASK(nk->n.width + nk->n.shift - 1, nk->n.shift); reg &= ~GENMASK(nk->k.width + nk->k.shift - 1, nk->k.shift); writel(reg | ((k - 1) << nk->k.shift) | ((n - 1) << nk->n.shift), nk->common.base + nk->common.reg); spin_unlock_irqrestore(nk->common.lock, flags); ccu_helper_wait_for_lock(&nk->common, nk->lock); return 0; }
static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct ccu_nm *nm = hw_to_ccu_nm(hw); unsigned long flags; unsigned long max_n, max_m; unsigned long n, m; u32 reg; if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) return ccu_frac_helper_set_rate(&nm->common, &nm->frac, rate); else ccu_frac_helper_disable(&nm->common, &nm->frac); max_n = 1 << nm->n.width; max_m = nm->m.max ?: 1 << nm->m.width; rational_best_approximation(rate, parent_rate, max_n, max_m, &n, &m); spin_lock_irqsave(nm->common.lock, flags); reg = readl(nm->common.base + nm->common.reg); reg &= ~GENMASK(nm->n.width + nm->n.shift - 1, nm->n.shift); reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift); writel(reg | ((m - 1) << nm->m.shift) | ((n - 1) << nm->n.shift), nm->common.base + nm->common.reg); spin_unlock_irqrestore(nm->common.lock, flags); ccu_helper_wait_for_lock(&nm->common, nm->lock); return 0; }
static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw); u32 n_mask, k_mask, m_mask, p_mask; struct _ccu_nkmp _nkmp; unsigned long flags; u32 reg; if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV) rate = rate * nkmp->fixed_post_div; _nkmp.min_n = nkmp->n.min ?: 1; _nkmp.max_n = nkmp->n.max ?: 1 << nkmp->n.width; _nkmp.min_k = nkmp->k.min ?: 1; _nkmp.max_k = nkmp->k.max ?: 1 << nkmp->k.width; _nkmp.min_m = 1; _nkmp.max_m = nkmp->m.max ?: 1 << nkmp->m.width; _nkmp.min_p = 1; _nkmp.max_p = nkmp->p.max ?: 1 << ((1 << nkmp->p.width) - 1); ccu_nkmp_find_best(parent_rate, rate, &_nkmp); n_mask = GENMASK(nkmp->n.width + nkmp->n.shift - 1, nkmp->n.shift); k_mask = GENMASK(nkmp->k.width + nkmp->k.shift - 1, nkmp->k.shift); m_mask = GENMASK(nkmp->m.width + nkmp->m.shift - 1, nkmp->m.shift); p_mask = GENMASK(nkmp->p.width + nkmp->p.shift - 1, nkmp->p.shift); spin_lock_irqsave(nkmp->common.lock, flags); reg = readl(nkmp->common.base + nkmp->common.reg); reg &= ~(n_mask | k_mask | m_mask | p_mask); reg |= ((_nkmp.n - nkmp->n.offset) << nkmp->n.shift) & n_mask; reg |= ((_nkmp.k - nkmp->k.offset) << nkmp->k.shift) & k_mask; reg |= ((_nkmp.m - nkmp->m.offset) << nkmp->m.shift) & m_mask; reg |= (ilog2(_nkmp.p) << nkmp->p.shift) & p_mask; writel(reg, nkmp->common.base + nkmp->common.reg); spin_unlock_irqrestore(nkmp->common.lock, flags); ccu_helper_wait_for_lock(&nkmp->common, nkmp->lock); return 0; }
static int ccu_mult_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct ccu_mult *cm = hw_to_ccu_mult(hw); struct _ccu_mult _cm; unsigned long flags; u32 reg; if (ccu_frac_helper_has_rate(&cm->common, &cm->frac, rate)) { ccu_frac_helper_enable(&cm->common, &cm->frac); return ccu_frac_helper_set_rate(&cm->common, &cm->frac, rate, cm->lock); } else { ccu_frac_helper_disable(&cm->common, &cm->frac); } parent_rate = ccu_mux_helper_apply_prediv(&cm->common, &cm->mux, -1, parent_rate); _cm.min = cm->mult.min; if (cm->mult.max) _cm.max = cm->mult.max; else _cm.max = (1 << cm->mult.width) + cm->mult.offset - 1; ccu_mult_find_best(parent_rate, rate, &_cm); spin_lock_irqsave(cm->common.lock, flags); reg = readl(cm->common.base + cm->common.reg); reg &= ~GENMASK(cm->mult.width + cm->mult.shift - 1, cm->mult.shift); reg |= ((_cm.mult - cm->mult.offset) << cm->mult.shift); writel(reg, cm->common.base + cm->common.reg); spin_unlock_irqrestore(cm->common.lock, flags); ccu_helper_wait_for_lock(&cm->common, cm->lock); return 0; }
static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct ccu_nm *nm = hw_to_ccu_nm(hw); struct _ccu_nm _nm; unsigned long flags; u32 reg; if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) return ccu_frac_helper_set_rate(&nm->common, &nm->frac, rate); else ccu_frac_helper_disable(&nm->common, &nm->frac); _nm.min_n = nm->n.min ?: 1; _nm.max_n = nm->n.max ?: 1 << nm->n.width; _nm.min_m = 1; _nm.max_m = nm->m.max ?: 1 << nm->m.width; ccu_nm_find_best(parent_rate, rate, &_nm); spin_lock_irqsave(nm->common.lock, flags); reg = readl(nm->common.base + nm->common.reg); reg &= ~GENMASK(nm->n.width + nm->n.shift - 1, nm->n.shift); reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift); reg |= (_nm.n - nm->n.offset) << nm->n.shift; reg |= (_nm.m - nm->m.offset) << nm->m.shift; writel(reg, nm->common.base + nm->common.reg); spin_unlock_irqrestore(nm->common.lock, flags); ccu_helper_wait_for_lock(&nm->common, nm->lock); return 0; }
static int ccu_nm_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct ccu_nm *nm = hw_to_ccu_nm(hw); struct _ccu_nm _nm; unsigned long flags; u32 reg; /* Adjust target rate according to post-dividers */ if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV) rate = rate * nm->fixed_post_div; if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) { spin_lock_irqsave(nm->common.lock, flags); /* most SoCs require M to be 0 if fractional mode is used */ reg = readl(nm->common.base + nm->common.reg); reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift); writel(reg, nm->common.base + nm->common.reg); spin_unlock_irqrestore(nm->common.lock, flags); ccu_frac_helper_enable(&nm->common, &nm->frac); return ccu_frac_helper_set_rate(&nm->common, &nm->frac, rate, nm->lock); } else { ccu_frac_helper_disable(&nm->common, &nm->frac); } _nm.min_n = nm->n.min ?: 1; _nm.max_n = nm->n.max ?: 1 << nm->n.width; _nm.min_m = 1; _nm.max_m = nm->m.max ?: 1 << nm->m.width; if (ccu_sdm_helper_has_rate(&nm->common, &nm->sdm, rate)) { ccu_sdm_helper_enable(&nm->common, &nm->sdm, rate); /* Sigma delta modulation requires specific N and M factors */ ccu_sdm_helper_get_factors(&nm->common, &nm->sdm, rate, &_nm.m, &_nm.n); } else { ccu_sdm_helper_disable(&nm->common, &nm->sdm); ccu_nm_find_best(parent_rate, rate, &_nm); } spin_lock_irqsave(nm->common.lock, flags); reg = readl(nm->common.base + nm->common.reg); reg &= ~GENMASK(nm->n.width + nm->n.shift - 1, nm->n.shift); reg &= ~GENMASK(nm->m.width + nm->m.shift - 1, nm->m.shift); reg |= (_nm.n - nm->n.offset) << nm->n.shift; reg |= (_nm.m - nm->m.offset) << nm->m.shift; writel(reg, nm->common.base + nm->common.reg); spin_unlock_irqrestore(nm->common.lock, flags); ccu_helper_wait_for_lock(&nm->common, nm->lock); return 0; }