int lpc313x_init_adc(void) { int dummy; u32 timeout; SYS_ADC_PD = 0; /* enable clock for ADC */ cgu_clk_en_dis(CGU_SB_ADC_CLK_ID, 1); cgu_clk_en_dis(CGU_SB_ADC_PCLK_ID, 1); /* reset to default */ ADC_CON_REG = ADC_CON_DEFAULT; ADC_CSEL_REG = ADC_CSEL_DEFAULT; ADC_INT_ENABLE_REG = ADC_INT_ENABLE_DEFAULT; ADC_INT_CLEAR_REG = ADC_INT_CLEAR_DEFAULT; /* dummy interupt status register read */ /** TODO: here we have to use a timeout, find out why and change, if neccessary. if you re-enable the adc the whole board freezes without this timeout. **/ dummy = ADC_INT_STATUS_REG; timeout = 0x2ffff; // if timeout is too high, we have to wait a bit (system freezes for this time) // for the driver while reenabling the adc. use 0x2fff. while((ADC_INT_STATUS_REG & 1) && timeout--); /* enable ADC interrupt */ ADC_INT_ENABLE_REG |= ADC_INT_ENABLE; /* set ADC power up */ ADC_CON_REG |= ADC_ENABLE; return 0; }
static inline void dma_decrement_usage(void) { if (!--dma_channels_requested) { cgu_clk_en_dis(CGU_SB_DMA_CLK_GATED_ID, 0); cgu_clk_en_dis(CGU_SB_DMA_PCLK_ID, 0); } }
/*-------------------------------------------------------------------------*/ int __init usbotg_init(void) { u32 bank = EVT_GET_BANK(EVT_usb_atx_pll_lock); u32 bit_pos = EVT_usb_atx_pll_lock & 0x1F; int retval = 0; /* enable USB to AHB clock */ cgu_clk_en_dis(CGU_SB_USB_OTG_AHB_CLK_ID, 1); /* enable clock to Event router */ cgu_clk_en_dis(CGU_SB_EVENT_ROUTER_PCLK_ID, 1); /* reset USB block */ cgu_soft_reset_module(USB_OTG_AHB_RST_N_SOFT); /* enable USB OTG PLL */ SYS_USB_ATX_PLL_PD_REG = 0x0; /* wait for PLL to lock */ while (!(EVRT_RSR(bank) & _BIT(bit_pos))); g_otg_dev.curr_dev = NULL; /* enable pull-up on ID pin so that we detect external pull-downs*/ USB_DEV_OTGSC |= OTGSC_IDPU; /* delay */ udelay(5); /* check ID state */ if (!(USB_DEV_OTGSC & OTGSC_STATUS(OTGSC_ID_INT))) { /* register host */ printk(KERN_INFO "Registering USB host 0x%08x 0x%08x (%d)\n", USB_DEV_OTGSC, EVRT_RSR(bank), bank); g_otg_dev.curr_dev = &ehci_lpc_device; g_otg_dev.current_state = OTG_STATE_A_IDLE; #ifndef CONFIG_MACH_BPS313XV1 lpc313x_vbus_power(1); #endif } else { /* register gadget */ printk(KERN_INFO "Registering USB gadget 0x%08x 0x%08x (%d)\n", USB_DEV_OTGSC, EVRT_RSR(bank), bank); #ifndef CONFIG_MACH_BPS313XV1 lpc313x_vbus_power(0); #endif g_otg_dev.curr_dev = &lpc313x_udc_device; g_otg_dev.current_state = OTG_STATE_B_IDLE; } if (0 == retval) { retval = platform_device_register(g_otg_dev.curr_dev); if ( 0 != retval ) printk(KERN_ERR "Can't register %s device\n", g_otg_dev.curr_dev->name); } #if 1 /* request IRQ to handle OTG events */ retval = request_irq(IRQ_USB, lpc313x_otg_irq, IRQF_SHARED, "OTG", &g_otg_dev); /* enable OTG interrupts */ USB_DEV_OTGSC |= OTGSC_INT_EN(OTGSC_ID_INT) | OTGSC_INT_STAT(OTGSC_ID_INT); #endif return retval; }
static int set_clock_stop(struct platform_device *pdev) { if (pdev->id) cgu_clk_en_dis( CGU_SB_I2C0_PCLK_ID, 0); else cgu_clk_en_dis( CGU_SB_I2C1_PCLK_ID, 0); return 0; }
static int set_clock_run(struct platform_device *pdev) { if (pdev->id) cgu_clk_en_dis( CGU_SB_I2C0_PCLK_ID, 1); else cgu_clk_en_dis( CGU_SB_I2C1_PCLK_ID, 1); udelay(2); return 0; }
void __init lpc313x_register_i2c_devices(void) { cgu_clk_en_dis( CGU_SB_I2C0_PCLK_ID, 1); cgu_clk_en_dis( CGU_SB_I2C1_PCLK_ID, 1); /* Enable I2C1 signals */ LPC313X_GPIO_DRV_IP(IOCONF_I2C1, 0x3); platform_add_devices(devices, ARRAY_SIZE(devices)); }
int lpc313x_deinit_adc(void) { /* wait while there is a conversion */ while (ADC_INT_STATUS_REG & 0x10); /* set ADC to default state */ ADC_CON_REG = ADC_CON_DEFAULT; ADC_CSEL_REG = ADC_CSEL_DEFAULT; ADC_INT_ENABLE_REG = ADC_INT_ENABLE_DEFAULT; ADC_INT_CLEAR_REG = ADC_INT_CLEAR_DEFAULT; /* disable clock for ADC */ cgu_clk_en_dis(CGU_SB_ADC_CLK_ID, 0); cgu_clk_en_dis(CGU_SB_ADC_PCLK_ID, 0); return 0; }
void __init lpc313x_register_i2c_devices(void) { cgu_clk_en_dis( CGU_SB_I2C0_PCLK_ID, 1); cgu_clk_en_dis( CGU_SB_I2C1_PCLK_ID, 1); /* Enable I2C1 signals */ GPIO_DRV_IP(IOCONF_I2C1, 0x3); #if defined (CONFIG_MACH_VAL3153) || defined (CONFIG_MACH_EA313X) /* on EA and VAL boards UDA1380 is connected to I2C1 * whose slave address is same as LPC313x's default slave * adress causing bus contention errors. So change the * deafult slave address register value of LPC313x here. */ LPC313x_I2C0_SLV_ADDR = 0x06E; LPC313x_I2C1_SLV_ADDR = 0x06E; #endif platform_add_devices(devices, ARRAY_SIZE(devices)); }
static void lpc313x_rng_endis_bus_clock(int enable) { cgu_clk_en_dis(CGU_SB_RNG_PCLK_ID, enable); }