uint32 cdp_cmd(UNIT * uptr, uint16 cmd, uint16 dev) { int chan = UNIT_G_CHAN(uptr->flags); int u = (uptr - cdp_unit); extern uint16 IC; if ((uptr->flags & UNIT_ATT) != 0 && cmd == IO_WRS) { /* Start device */ if (!(uptr->u5 & CDPSTA_CMD)) { dev_pulse[chan] &= ~PUNCH_M; uptr->u5 &= ~CDPSTA_PUNCH; if ((uptr->u5 & CDPSTA_ON) == 0) { uptr->wait = 330; /* Startup delay */ } else if (uptr->u5 & CDPSTA_IDLE && uptr->wait <= 30) { uptr->wait += 85; /* Wait for next latch point */ } uptr->u5 |= (CDPSTA_WRITE | CDPSTA_CMD); uptr->u5 &= ~CDPSTA_POSMASK; chan_set_sel(chan, 1); chan_clear_status(chan); sim_activate(uptr, us_to_ticks(1000)); /* activate */ sim_debug(DEBUG_CMD, &cdp_dev, "%05o WRS unit=%d\n", IC, u); return SCPE_OK; } } chan_set_attn(chan); return SCPE_IOERR; }
/* Handle transfer of data for card reader */ t_stat cdr_srv(UNIT *uptr) { int chan = UNIT_G_CHAN(uptr->flags); int u = (uptr - cdr_unit); uint16 *image = (uint16 *)(uptr->up7); /* Waiting for disconnect */ if (uptr->u5 & URCSTA_WDISCO) { if (chan_stat(chan, DEV_DISCO)) { chan_clear(chan, DEV_SEL|DEV_WEOR); uptr->u5 &= ~ URCSTA_WDISCO; } else { /* No disco yet, try again in a bit */ sim_activate(uptr, 50); return SCPE_OK; } /* If still busy, schedule another wait */ if (uptr->u5 & URCSTA_BUSY) sim_activate(uptr, uptr->wait); } if (uptr->u5 & URCSTA_BUSY) { uptr->u5 &= ~URCSTA_BUSY; #ifdef I7070 switch(uptr->flags & (ATTENA|ATTENB)) { case ATTENA: chan_set_attn_a(chan); break; case ATTENB: chan_set_attn_b(chan); break; } #endif } /* Check if new card requested. */ if (uptr->u4 == 0 && uptr->u5 & URCSTA_READ && (uptr->u5 & URCSTA_CARD) == 0) { switch(sim_read_card(uptr, image)) { case CDSE_EOF: sim_debug(DEBUG_DETAIL, &cdr_dev, "%d: EOF\n", u); /* Fall through */ case CDSE_EMPTY: chan_set_eof(chan); chan_set_attn(chan); chan_clear(chan, DEV_SEL); uptr->u5 |= URCSTA_EOF; uptr->u5 &= ~(URCSTA_BUSY|URCSTA_READ); return SCPE_OK; case CDSE_ERROR: sim_debug(DEBUG_DETAIL, &cdr_dev, "%d: ERF\n", u); uptr->u5 |= URCSTA_ERR; uptr->u5 &= ~(URCSTA_BUSY|URCSTA_READ); chan_set_attn(chan); chan_clear(chan, DEV_SEL); return SCPE_OK; case CDSE_OK: uptr->u5 |= URCSTA_CARD; #ifdef I7010 chan_set_attn_urec(chan, cdr_dib.addr); #endif break; } #ifdef I7070 /* Check if load card. */ if (uptr->capac && (image[uptr->capac-1] & 0x800)) { uptr->u5 |= URCSTA_LOAD; chan_set_load_mode(chan); } else { uptr->u5 &= ~URCSTA_LOAD; } #endif } if (uptr->u5 & URCSTA_NOXFER) { uptr->u5 &= ~(URCSTA_NOXFER|URCSTA_READ); return SCPE_OK; } /* Copy next column over */ if (uptr->u5 & URCSTA_READ && uptr->u4 < 80) { uint8 ch = 0; #ifdef I7080 /* Detect RSU */ if (image[uptr->u4] == 0x924) { uptr->u5 &= ~URCSTA_READ; uptr->u5 |= URCSTA_WDISCO; chan_set(chan, DEV_REOR); sim_activate(uptr, 10); return SCPE_OK; } #endif ch = sim_hol_to_bcd(image[uptr->u4]); /* Handle invalid punch */ if (ch == 0x7f) { #ifdef I7080 uptr->u5 &= ~(URCSTA_READ|URCSTA_BUSY); sim_debug(DEBUG_DETAIL, &cdr_dev, "%d: bad punch %d\n", u, uptr->u4); chan_set_attn(chan); chan_set_error(chan); chan_clear(chan, DEV_SEL); #else uptr->u5 |= URCSTA_ERR; ch = 017; #endif } #ifdef I7070 /* During load, only sign on every 10 columns */ if (uptr->u5 & URCSTA_LOAD && (uptr->u4 % 10) != 9) ch &= 0xf; #endif switch(chan_write_char(chan, &ch, (uptr->u4 == 79)? DEV_REOR: 0)) { case TIME_ERROR: case END_RECORD: uptr->u5 |= URCSTA_WDISCO|URCSTA_BUSY; uptr->u5 &= ~URCSTA_READ; break; case DATA_OK: uptr->u4++; break; } sim_debug(DEBUG_DATA, &cdr_dev, "%d: Char > %02o\n", u, ch); sim_activate(uptr, 10); } return SCPE_OK; }
/* * Device entry points for card reader. */ uint32 cdr_cmd(UNIT * uptr, uint16 cmd, uint16 dev) { int chan = UNIT_G_CHAN(uptr->flags); int u = (uptr - cdr_unit); int stk = dev & 017; /* Are we currently tranfering? */ if (uptr->u5 & URCSTA_READ) return SCPE_BUSY; /* Test ready */ if (cmd == IO_TRS && uptr->flags & UNIT_ATT) { sim_debug(DEBUG_CMD, &cdr_dev, "%d: Test Rdy\n", u); return SCPE_OK; } if (stk == 10) stk = 0; #ifdef STACK_DEV uptr->u5 &= ~0xF0000; uptr->u5 |= stk << 16; #endif if (uptr->u5 & (URCSTA_EOF|URCSTA_ERR)) return SCPE_IOERR; /* Process commands */ switch(cmd) { case IO_RDS: sim_debug(DEBUG_CMD, &cdr_dev, "%d: Cmd RDS %02o\n", u, dev & 077); #ifdef I7010 if (stk!= 9) #endif uptr->u5 &= ~(URCSTA_CARD|URCSTA_ERR); break; case IO_CTL: sim_debug(DEBUG_CMD, &cdr_dev, "%d: Cmd CTL %02o\n", u, dev & 077); #ifdef I7010 uptr->u5 |= URCSTA_NOXFER; #endif break; default: chan_set_attn(chan); return SCPE_IOERR; } /* If at eof, just return EOF */ if (uptr->u5 & URCSTA_EOF) { chan_set_eof(chan); chan_set_attn(chan); return SCPE_OK; } uptr->u5 |= URCSTA_READ; uptr->u4 = 0; if ((uptr->u5 & URCSTA_NOXFER) == 0) chan_set_sel(chan, 0); /* Wake it up if not busy */ if ((uptr->u5 & URCSTA_BUSY) == 0) sim_activate(uptr, 50); return SCPE_OK; }