static void __clk_enable(struct clk *clk)
{
if (!clk)
return;
/* enable parent clock first */
if (clk->parent)
__clk_enable(clk->parent);
if (clk->use_cnt++ == 0) {
if (clk_is_pll1(clk)) { /* PLL1 */
chipcHw_pll1Enable(clk->rate_hz, 0);
} else if (clk_is_pll2(clk)) { /* PLL2 */
chipcHw_pll2Enable(clk->rate_hz);
} else if (clk_is_using_xtal(clk)) { /* source is crystal */
if (!clk_is_primary(clk))
chipcHw_bypassClockEnable(clk->csp_id);
} else { /* source is PLL */
chipcHw_setClockEnable(clk->csp_id);
}
}
}
static void __clk_enable(struct clk *clk)
{
if (!clk)
return;
if (clk->parent)
__clk_enable(clk->parent);
if (clk->use_cnt++ == 0) {
if (clk_is_pll1(clk)) {
chipcHw_pll1Enable(clk->rate_hz, 0);
} else if (clk_is_pll2(clk)) {
chipcHw_pll2Enable(clk->rate_hz);
} else if (clk_is_using_xtal(clk)) {
if (!clk_is_primary(clk))
chipcHw_bypassClockEnable(clk->csp_id);
} else {
chipcHw_setClockEnable(clk->csp_id);
}
}
}