static void bootblock_southbridge_init(void) { ck804_enable_rom(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 (0xa<<3)|4, (0xa<<3)|6, 0, 0, (0xa<<3)|5, (0xa<<3)|7, 0, 0, #endif }; int needs_reset; unsigned bsp_apicid = 0; struct mem_controller ctrl[8]; unsigned nodes; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); /* Setup the ck804 */ ck804_enable_rom(); } if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx); } // post_code(0x32); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); setup_s2891_resource_map(); #if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif needs_reset |= ht_setup_chains_x(); needs_reset |= ck804_early_setup_x(); if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); nodes = get_nodes(); //It's the time to set ctrl now; fill_mem_ctrl(nodes, ctrl, spd_addr); enable_smbus(); #if 0 dump_spd_registers(&cpu[0]); #endif #if 0 dump_smbus_registers(); #endif memreset_setup(); sdram_initialize(nodes, ctrl); #if 0 print_pci_devices(); #endif #if 0 dump_pci_devices(); #endif post_cache_as_ram(); }