int appf_setup_translation_tables(void)
{
unsigned firmware_start_pa, firmware_start_va,attr;
unsigned tab1_pa,pa;
int i;
firmware_start_va = ((unsigned)&main_table) & PAGE_MASK;
firmware_start_pa = reloc_addr(firmware_start_va);
tab1_pa = reloc_addr((unsigned)appf_translation_table1);
// tex_remap = read_sctlr() & TRE_MASK;/* TRE: 0:remap disable, 1: remap enable*/
for (i = 0; i < 4096; ++i)
{
if(i == 0x04f)
attr = 0xc0e;
else if(i <=0x3FF)
attr = 0x10c02;
else if( i < 0x40F)
attr = 0xc0e;
else if( i == 0x490)
attr = 0xc0e;
else if(i == 0x498)
attr = 0xc0e;
else if(i >= 0x800 && i <= 0x9FF)
attr = 0xc0e;
else if(i >= 0xa00 && i <= 0xbff)
attr = 0x10c02;
else if(i == 0xc11)
attr = 0x10412;
else if(i == 0xc12)
attr = 0x10412;
else if(i == 0xc42)
attr = 0x412;
else if(i==0xc43)
attr = 0x2412;
else if(i>=0xc80 && i <= 0xCFF)
attr = 0x412;
else if(i>=0xe00 && i <= 0xfff)
attr = 0xc0e;
else
attr = 0;
if(i >= 0xC00 && i <= 0xC06)
{
((unsigned*)tab1_pa) [i] = 0xc0e|((0x800 + (i - 0xc00))<<20);
}
else if(i >= 0xD00 & i < 0xDFF)
{
((unsigned*)tab1_pa) [i] = 0xc0e|((0x900 + (i - 0xD00))<<20);
}
else if(i == 0xc4F)
{
((unsigned*)tab1_pa) [i] = 0x402|(0x04F<<20);//0xc0e
}
else if(i == 0xc4D)
{
((unsigned*)tab1_pa) [i] = 0x402|(0x04F<<20);//0xc0e
}
else if(i == 0xCFF)
{
((unsigned*)tab1_pa) [i] = 0xc0e|(0xFF<<20);
}
else if(i == 0xF11)
((unsigned*)tab1_pa) [i] = 0x412|(0xC11<<20);
else if(i == 0xF13)
((unsigned*)tab1_pa) [i] = 0x412|(0xC13<<20);
else if(i == 0xF22)
((unsigned*)tab1_pa) [i] = 0x412|(0xC42<<20);
else if(i == 0xF23)
((unsigned*)tab1_pa) [i] = 0x412|(0xC43<<20);
else if(i == 0xF30)
((unsigned*)tab1_pa) [i] = 0x412|(0xC80<<20);
else if(i == 0xF31)
((unsigned*)tab1_pa) [i] = 0x412|(0xC81<<20);
else if(i == 0xF32)
((unsigned*)tab1_pa) [i] = 0x412|(0xC90<<20);
else if(i == 0xF40)
((unsigned*)tab1_pa) [i] = 0x412|(0xCC0<<20);
else if(i == 0xF80)
((unsigned*)tab1_pa) [i] = 0x412|(0xd00<<20);
else if(i == 0xF90)
((unsigned*)tab1_pa) [i] = 0x412|(0xd90<<20);
else if(i == 0xFA0)
((unsigned*)tab1_pa) [i] = 0x412|(0xda0<<20);
else
((unsigned*)tab1_pa) [i] = attr|(i<<20);
}
// ((unsigned*)tab1_pa)[firmware_start_va >> SECTION_SHIFT] = reloc_addr((unsigned)appf_translation_table2a) | PAGE_TABLE;
// ((unsigned*)tab1_pa)[firmware_start_pa >> SECTION_SHIFT] = reloc_addr((unsigned)appf_translation_table2b) | PAGE_TABLE;
pa = reloc_addr((unsigned)&appf_ttbr0);
*((volatile unsigned*)pa) = reloc_addr((unsigned)appf_translation_table1);
__V(appf_ttbcr) = 0;
clean_dcache_v7_l1();
return APPF_OK;
}
/**
* This function saves all the context that will be lost
* when a CPU and cluster enter a low power state.
*/
static void platform_save_context(struct cpu_cluster *cluster, struct cpu *pcpu)
{
struct cpu_context *context = &(pcpu->context);
struct cpu_cluster_context *cluster_context = &(cluster->context);
#if MAX_CPUS != 1
int cluster_down = 0;
#endif
/* Save perf. monitors first, so we don't interfere too much with counts */
save_performance_monitors(context->pmu_data);
save_a9_timers(context->timer_data, cluster->scu_address);
save_vfp(context->vfp_data);
save_gic_interface(context->gic_interface_data, pcpu->ic_address);
save_gic_distributor_private(context->gic_dist_private_data, cluster->ic_address);
save_cp15(context->cp15_data);
save_a9_other(context->other_data);
#if 0 //wschen 2011-07-28
save_a9_debug(context->debug_data);
#endif
#if MAX_CPUS != 1
if (cluster->power_state >= STATUS_DORMANT) {
cluster_down = 1;
}
#endif
#if MAX_CPUS != 1
if (cluster_down) {
#endif
save_a9_global_timer(cluster_context->global_timer_data, cluster->scu_address);
save_gic_distributor_shared(cluster_context->gic_dist_shared_data, cluster->ic_address);
#if MAX_CPUS != 1
}
#endif
save_control_registers(context);
save_mmu(context->mmu_data);
#if MAX_CPUS != 1
if (cluster_down) {
#endif
save_a9_scu(cluster_context->scu_data, cluster->scu_address);
save_pl310(cluster_context->l2_data, cluster->l2_address);
#if MAX_CPUS != 1
}
#endif
dormant_ret_flag = 0;
save_banked_registers(context->banked_registers);
if (dormant_ret_flag == 0) {
clean_dcache_v7_l1();
clean_pl310(cpu_cluster.l2_address);
if (e1_chip) {
disable_pl310(cpu_cluster.l2_address);
disable_cache_v7_l1();
if (cpu_cluster.power_state == STATUS_DORMANT) {
reg_write(SC_PWR_CON0, 0xE105); /* SRAM sleep */
} else {
reg_write(SC_PWR_CON0, 0xC12D); /* SRAM power down */
}
dsb();
if (cpu_cluster.power_state == STATUS_DORMANT) {
reg_write(SC_PWR_CON2, 0xE505); /* SRAM sleep */
} else {
reg_write(SC_PWR_CON2, 0xC52D); /* SRAM power down */
}
dsb();
}
return;
} else {
return;
}
}