int __init am33xx_clk_init(void) { struct omap_clk *c; u32 cpu_clkflg; if (soc_is_am33xx()) { cpu_mask = RATE_IN_AM33XX; cpu_clkflg = CK_AM33XX; } clk_init(&omap2_clk_functions); for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) clk_preinit(c->lk.clk); for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) { if (c->cpu & cpu_clkflg) { clkdev_add(&c->lk); clk_register(c->lk.clk); omap2_init_clk_clkdm(c->lk.clk); } } recalculate_root_clocks(); /* * Only enable those clocks we will need, let the drivers * enable other clocks as necessary */ clk_enable_init_clocks(); return 0; }
int __init clk_init(void) { int ret; ret = arch_clk_init(); if (unlikely(ret)) { pr_err("%s: CPU clock registration failed.\n", __func__); return ret; } if (sh_mv.mv_clk_init) { ret = sh_mv.mv_clk_init(); if (unlikely(ret)) { pr_err("%s: machvec clock initialization failed.\n", __func__); return ret; } } /* Kick the child clocks.. */ recalculate_root_clocks(); /* Enable the necessary init clocks */ clk_enable_init_clocks(); return ret; }
int __init clk_init(void) { int ret; ret = arch_clk_init(); if (unlikely(ret)) { pr_err("%s: CPU clock registration failed.\n", __func__); return ret; } if (sh_mv.mv_clk_init) { ret = sh_mv.mv_clk_init(); if (unlikely(ret)) { pr_err("%s: machvec clock initialization failed.\n", __func__); return ret; } } recalculate_root_clocks(); clk_enable_init_clocks(); return ret; }
int __init omap2_clk_init(void) { struct prcm_config *prcm; struct omap_clk *c; u32 clkrate; if (cpu_is_omap242x()) cpu_mask = RATE_IN_242X; else if (cpu_is_omap2430()) cpu_mask = RATE_IN_243X; clk_init(&omap2_clk_functions); for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) clk_init_one(c->lk.clk); osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); propagate_rate(&osc_ck); sys_ck.rate = omap2_sys_clk_recalc(&sys_ck); propagate_rate(&sys_ck); for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) if (c->cpu & cpu_mask) { clkdev_add(&c->lk); clk_register(c->lk.clk); } /* Check the MPU rate set by bootloader */ clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); for (prcm = rate_table; prcm->mpu_speed; prcm++) { if (!(prcm->flags & cpu_mask)) continue; if (prcm->xtal_speed != sys_ck.rate) continue; if (prcm->dpll_speed <= clkrate) break; } curr_prcm_set = prcm; recalculate_root_clocks(); printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): " "%ld.%01ld/%ld/%ld MHz\n", (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; /* * Only enable those clocks we will need, let the drivers * enable other clocks as necessary */ clk_enable_init_clocks(); /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ vclk = clk_get(NULL, "virt_prcm_set"); sclk = clk_get(NULL, "sys_ck"); return 0; }
int __init omap2_clk_init(void) { /* struct prcm_config *prcm; */ struct clk **clkp; /* u32 clkrate; */ u32 cpu_clkflg; /* REVISIT: Ultimately this will be used for multiboot */ #if 0 if (cpu_is_omap242x()) { cpu_mask = RATE_IN_242X; cpu_clkflg = CLOCK_IN_OMAP242X; clkp = onchip_24xx_clks; } else if (cpu_is_omap2430()) { cpu_mask = RATE_IN_243X; cpu_clkflg = CLOCK_IN_OMAP243X; clkp = onchip_24xx_clks; } #endif if (cpu_is_omap34xx()) { cpu_mask = RATE_IN_343X; cpu_clkflg = CLOCK_IN_OMAP343X; clkp = onchip_34xx_clks; /* * Update this if there are further clock changes between ES2 * and production parts */ if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0)) { /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ cpu_clkflg |= CLOCK_IN_OMAP3430ES1; } else { cpu_mask |= RATE_IN_3430ES2; cpu_clkflg |= CLOCK_IN_OMAP3430ES2; } } clk_init(&omap2_clk_functions); for (clkp = onchip_34xx_clks; clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks); clkp++) { if ((*clkp)->flags & cpu_clkflg) clk_register(*clkp); } /* REVISIT: Not yet ready for OMAP3 */ #if 0 /* Check the MPU rate set by bootloader */ clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); for (prcm = rate_table; prcm->mpu_speed; prcm++) { if (!(prcm->flags & cpu_mask)) continue; if (prcm->xtal_speed != sys_ck.rate) continue; if (prcm->dpll_speed <= clkrate) break; } curr_prcm_set = prcm; #endif recalculate_root_clocks(); printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): " "%ld.%01ld/%ld/%ld MHz\n", (osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10, (core_ck.rate / 1000000), (arm_fck.rate / 1000000)); /* * Only enable those clocks we will need, let the drivers * enable other clocks as necessary */ clk_enable_init_clocks(); /* Avoid sleeping during omap2_clk_prepare_for_reboot() */ /* REVISIT: not yet ready for 343x */ #if 0 vclk = clk_get(NULL, "virt_prcm_set"); sclk = clk_get(NULL, "sys_ck"); #endif return 0; }
int __init omap2_clk_init(void) { struct prcm_config *prcm; struct clk **clkp; u32 clkrate; if (cpu_is_omap242x()) cpu_mask = RATE_IN_242X; else if (cpu_is_omap2430()) cpu_mask = RATE_IN_243X; clk_init(&omap2_clk_functions); omap2_osc_clk_recalc(&osc_ck, 0, CURRENT_RATE); omap2_sys_clk_recalc(&sys_ck, sys_ck.parent->rate, CURRENT_RATE); for (clkp = onchip_24xx_clks; clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks); clkp++) { if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) { clk_register(*clkp); continue; } if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) { clk_register(*clkp); continue; } } /* Check the MPU rate set by bootloader */ clkrate = omap2xxx_clk_get_core_rate(&dpll_ck, dpll_ck.parent->rate); for (prcm = rate_table; prcm->mpu_speed; prcm++) { if (!(prcm->flags & cpu_mask)) continue; if (prcm->xtal_speed != sys_ck.rate) continue; if (prcm->dpll_speed <= clkrate) break; } curr_prcm_set = prcm; recalculate_root_clocks(); printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): " "%ld.%01ld/%ld/%ld MHz\n", (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; /* * Only enable those clocks we will need, let the drivers * enable other clocks as necessary */ clk_enable_init_clocks(); /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ vclk = clk_get(NULL, "virt_prcm_set"); sclk = clk_get(NULL, "sys_ck"); return 0; }