static void exynos_audss_clk_teardown(void) { int i; for (i = EXYNOS_MOUT_AUDSS; i < EXYNOS_DOUT_SRP; i++) { if (!IS_ERR(clk_table[i])) clk_unregister_mux(clk_table[i]); } for (; i < EXYNOS_SRP_CLK; i++) { if (!IS_ERR(clk_table[i])) clk_unregister_divider(clk_table[i]); } for (; i < clk_data.clk_num; i++) { if (!IS_ERR(clk_table[i])) clk_unregister_gate(clk_table[i]); } }
int hisi_clk_register_mux(const struct hisi_mux_clock *clks, int nums, struct hisi_clock_data *data) { struct clk *clk; void __iomem *base = data->base; int i; for (i = 0; i < nums; i++) { u32 mask = BIT(clks[i].width) - 1; clk = clk_register_mux_table(NULL, clks[i].name, clks[i].parent_names, clks[i].num_parents, clks[i].flags, base + clks[i].offset, clks[i].shift, mask, clks[i].mux_flags, clks[i].table, &hisi_clk_lock); if (IS_ERR(clk)) { pr_err("%s: failed to register clock %s\n", __func__, clks[i].name); goto err; } if (clks[i].alias) clk_register_clkdev(clk, clks[i].alias, NULL); data->clk_data.clks[clks[i].id] = clk; } return 0; err: while (i--) clk_unregister_mux(data->clk_data.clks[clks[i].id]); return PTR_ERR(clk); }