void disp_bls_init(unsigned int srcWidth, unsigned int srcHeight)
{
DDP_DRV_DBG("disp_bls_init : srcWidth = %d, srcHeight = %d\n", srcWidth, srcHeight);
struct cust_mt65xx_led *cust_led_list = get_cust_led_list();
struct cust_mt65xx_led *cust = NULL;
struct PWM_config *config_data = NULL;
if(cust_led_list)
{
cust = &cust_led_list[MT65XX_LED_TYPE_LCD];
if((strcmp(cust->name,"lcd-backlight") == 0) && (cust->mode == MT65XX_LED_MODE_CUST_BLS_PWM))
{
config_data = &cust->config_data;
if (config_data->clock_source >= 0 && config_data->clock_source <= 1)
{
unsigned int regVal = DISP_REG_GET(0xF0000000);
if(config_data->clock_source == 0)
clkmux_sel(MT_CLKMUX_PWM_MM_MUX_SEL, MT_CG_SYS_26M, "DISP_PWM");
else
clkmux_sel(MT_CLKMUX_PWM_MM_MUX_SEL, MT_CG_UPLL_D12, "DISP_PWM");
DISP_DBG("disp_bls_init : 0xF0000000: 0x%x => 0x%x\n", regVal, DISP_REG_GET(0xF0000000));
}
}
}
// TODO: fix register setting
DISP_REG_SET(DISP_REG_BLS_SRC_SIZE, (srcHeight << 16) | srcWidth);
DISP_REG_SET(DISP_REG_BLS_PWM_DUTY, DISP_REG_GET(DISP_REG_BLS_PWM_DUTY));
DISP_REG_SET(DISP_REG_BLS_PWM_CON, 0x0);
DISP_REG_SET(DISP_REG_BLS_INTEN, 0xF);
disp_bls_update_gamma_lut();
//disp_bls_update_pwm_lut(); // not used in 6572
#if 0 // TODO: fix Dither setting
// Dithering
DISP_REG_SET(DISP_REG_BLS_DITHER(0), 0x00000001);
DISP_REG_SET(DISP_REG_BLS_DITHER(6), 0x00000000);
DISP_REG_SET(DISP_REG_BLS_DITHER(13), 0x00000222);
DISP_REG_SET(DISP_REG_BLS_DITHER(14), 0x00000000);
DISP_REG_SET(DISP_REG_BLS_DITHER(15), 0x22220001);
DISP_REG_SET(DISP_REG_BLS_DITHER(16), 0x22222222);
DISP_REG_SET(DISP_REG_BLS_DITHER(17), 0x00000000);
#endif
DISP_REG_SET(DISP_REG_BLS_EN, 0x00010001); // enable BLS_EN
disp_bls_config_full(srcWidth, srcHeight);
#if 0
disp_dump_reg(DISP_MODULE_BLS);
#endif
}
void disp_set_pll(unsigned int freq)
{
unsigned long reg_va_con0 = 0;
unsigned long reg_va_con1 = 0;
static unsigned int freq_last = 364;
static unsigned int pll_cnt;
if (freq == freq_last)
return;
freq_last = freq;
reg_va_con0 =
(unsigned long)ioremap_nocache(REG_PA_VENC_PLL_CON0,
sizeof(unsigned long));
reg_va_con1 =
(unsigned long)ioremap_nocache(REG_PA_VENC_PLL_CON1,
sizeof(unsigned long));
pr_debug
("disp_set_pll(%d), before set, con0=0x%x, con1=0x%x, 0x%lx, 0x%lx\n",
freq, DISP_REG_GET(reg_va_con0), DISP_REG_GET(reg_va_con1),
reg_va_con0, reg_va_con1);
if (freq == 156) {
enable_pll(VENCPLL, DISP_CLOCK_USER_NAME);
DISP_CPU_REG_SET(reg_va_con0, DISP_MMCLK_156MHZ_CON0);
DISP_CPU_REG_SET(reg_va_con1, DISP_MMCLK_156MHZ_CON1);
clkmux_sel(MT_MUX_MM, 3, DISP_CLOCK_USER_NAME);
pll_cnt++;
} else if (freq == 182) {
enable_pll(VENCPLL, DISP_CLOCK_USER_NAME);
DISP_CPU_REG_SET(reg_va_con0, DISP_MMCLK_182MHZ_CON0);
DISP_CPU_REG_SET(reg_va_con1, DISP_MMCLK_182MHZ_CON1);
clkmux_sel(MT_MUX_MM, 3, DISP_CLOCK_USER_NAME);
pll_cnt++;
} else if (freq == 364) {
clkmux_sel(MT_MUX_MM, 1, DISP_CLOCK_USER_NAME);
if (pll_cnt != 0) {
disable_pll(VENCPLL, DISP_CLOCK_USER_NAME);
pll_cnt--;
}
} else {
pr_debug("disp_set_pll, error, invalid freq=%d\n", freq);
}
pr_debug("disp_set_pll(%d), after set, con0=0x%x, con1=0x%x\n",
freq, DISP_REG_GET(reg_va_con0), DISP_REG_GET(reg_va_con1));
iounmap((void *)reg_va_con0);
iounmap((void *)reg_va_con1);
}
void DPI_MIPI_clk_setting(unsigned int mipi_pll_clk_ref,unsigned int mipi_pll_clk_div1,unsigned int mipi_pll_clk_div2){
UINT32 i, j;
UINT32 txdiv0 = 0;
UINT32 txdiv1 = 0;
UINT32 posdiv = 0;
UINT32 prediv = 0;
UINT32 txmul = 0;
UINT32 sdm_ssc_en = 0;
UINT32 sdm_ssc_prd = 0; // 0~65535
UINT32 sdm_ssc_delta1 = 0; // 0~65535
UINT32 sdm_ssc_delta = 0; // 0~65535
UINT32 loopback_en = 0;
UINT32 lane0_en = 1;
UINT32 lane1_en = 1;
UINT32 lane2_en = 1;
UINT32 lane3_en = 1;
txmul = mipi_pll_clk_ref ;
posdiv = mipi_pll_clk_div1;
prediv = mipi_pll_clk_div2;
clkmux_sel(MT_MUX_DPI0, txmul, "DPI0");
OUTREG32(TVDPLL_CON0, posdiv); ///pll
OUTREG32(TVDPLL_CON1, prediv); //pll
///pll_fsel(TVDPLL, prediv);
///OUTREG32(TVDPLL_CON0, 0x131); ///pll
///OUTREG32(TVDPLL_CON1, 0x800B6C4F); //pll
printk("[DPI] MIPIPLL Exit\n");
}
static void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl)
{
/* enable PCM WDT (normal mode) to start count if needed */
#if SPM_PCMWDT_EN
{
u32 con1;
con1 = spm_read(SPM_PCM_CON1) & ~(CON1_PCM_WDT_WAKE_MODE | CON1_PCM_WDT_EN);
spm_write(SPM_PCM_CON1, CON1_CFG_KEY | con1);
if (spm_read(SPM_PCM_TIMER_VAL) > PCM_TIMER_MAX)
spm_write(SPM_PCM_TIMER_VAL, PCM_TIMER_MAX);
spm_write(SPM_PCM_WDT_TIMER_VAL, spm_read(SPM_PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
spm_write(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_PCM_WDT_EN);
}
#endif
#if SPM_PCMTIMER_DIS
{
u32 con1; //CONFIG_MTK_LDVT is enable? Otherwise why con1: /mt_spm_sleep.c:523:9: error: 'con1' undeclared (first use in this function)
con1 = spm_read(SPM_PCM_CON1) & ~(CON1_PCM_TIMER_EN);
spm_write(SPM_PCM_CON1, con1 | CON1_CFG_KEY);
}
#endif
/* init PCM_PASR_DPD_0 for DPD */
spm_write(SPM_PCM_PASR_DPD_0, 0);
//FIXME: for K2 fpga early porting
#if 0
/* make MD32 work in suspend: fscp_ck = CLK26M */
clkmux_sel(MT_MUX_SCP, 0, "SPM-Sleep");
#endif
__spm_kick_pcm_to_run(pwrctrl);
}
void AudDrv_APLL24M_Clk_Off(void)
{
mutex_lock(&auddrv_pmic_mutex);
Aud_APLL24M_Clk_cntr--;
if (Aud_APLL24M_Clk_cntr == 0)
{
PRINTK_AUDDRV("+%s disable_clock ADC clk(%x)\n", __func__, Aud_APLL24M_Clk_cntr);
#ifdef PM_MANAGER_API
if (disable_clock(MT_CG_AUDIO_24M, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
if (disable_clock(MT_CG_AUDIO_APLL2_TUNER, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
clkmux_sel(MT_MUX_AUD2, 0, "AUDIO"); //select 26M
disable_mux(MT_MUX_AUD2, "AUDIO");
#endif
}
if (Aud_APLL24M_Clk_cntr < 0)
{
PRINTK_AUDDRV("%s <0 (%d) \n", __func__, Aud_APLL24M_Clk_cntr);
Aud_APLL24M_Clk_cntr = 0;
}
mutex_unlock(&auddrv_pmic_mutex);
}
void spm_dpidle_before_wfi(void)
{
int err = 0;
g_clk_aud_intbus_sel = clkmux_get(MT_CLKMUX_AUD_INTBUS_SEL,"Deep_Idle");
clkmux_sel(MT_CLKMUX_AUD_INTBUS_SEL, MT_CG_SYS_26M,"Deep_Idle");
enable_clock(MT_CG_PMIC_SW_CG_AP, "DEEP_IDLE");//PMIC CG bit for AP. SPM need PMIC wrapper clock to change Vcore voltage
#ifdef CONFIG_SMP
free_gpt(GPT4);
err = request_gpt(GPT4, GPT_ONE_SHOT, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1,
0, NULL, GPT_NOAUTOEN);
if (err) {
idle_info("[%s]fail to request GPT4\n", __func__);
}
dpidle_timer_left2 = localtimer_get_counter();
if( dpidle_timer_left2 <=0 )
gpt_set_cmp(GPT4, 1);//Trigger GPT4 Timerout imediately
else
gpt_set_cmp(GPT4, dpidle_timer_left2);
start_gpt(GPT4);
#else
gpt_get_cnt(GPT1, &dpidle_timer_left2);
#endif
}
void spm_dpidle_after_wfi(void)
{
#ifdef CONFIG_SMP
//if (gpt_check_irq(GPT4)) {
if (gpt_check_and_ack_irq(GPT4)) {
/* waked up by WAKEUP_GPT */
localtimer_set_next_event(1);
} else {
/* waked up by other wakeup source */
unsigned int cnt, cmp;
gpt_get_cnt(GPT4, &cnt);
gpt_get_cmp(GPT4, &cmp);
if (unlikely(cmp < cnt)) {
idle_err("[%s]GPT%d: counter = %10u, compare = %10u\n", __func__,
GPT4 + 1, cnt, cmp);
BUG();
}
localtimer_set_next_event(cmp-cnt);
stop_gpt(GPT4);
//GPT_ClearCount(WAKEUP_GPT);
free_gpt(GPT4);
}
#endif
disable_clock(MT_CG_PMIC_SW_CG_AP, "DEEP_IDLE");
clkmux_sel(MT_CLKMUX_AUD_INTBUS_SEL,g_clk_aud_intbus_sel,"Deep_Idle");
dpidle_cnt[0]++;
}
static void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl)
{
/* enable PCM WDT (normal mode) to start count if needed */
#if SPM_PCMWDT_EN
{
u32 con1;
con1 = spm_read(SPM_PCM_CON1) & ~(CON1_PCM_WDT_WAKE_MODE | CON1_PCM_WDT_EN);
// PCM WDT WAKE MODE for lastPC
// con1 = spm_read(SPM_PCM_CON1) & ~( CON1_PCM_WDT_EN) | CON1_PCM_WDT_WAKE_MODE;
spm_write(SPM_PCM_CON1, CON1_CFG_KEY | con1);
if (spm_read(SPM_PCM_TIMER_VAL) > PCM_TIMER_MAX)
spm_write(SPM_PCM_TIMER_VAL, PCM_TIMER_MAX);
spm_write(SPM_PCM_WDT_TIMER_VAL, spm_read(SPM_PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
spm_write(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_PCM_WDT_EN);
}
#endif
/* init PCM_PASR_DPD_0 for DPD */
spm_write(SPM_PCM_PASR_DPD_0, 0);
/* make MD32 work in suspend: fscp_ck = CLK26M */
clkmux_sel(MT_MUX_SCP, 0, "SPM-Sleep");
__spm_kick_pcm_to_run(pwrctrl);
}
void AudDrv_APLL22M_Clk_On(void)
{
PRINTK_AUD_CLK("+%s %d \n", __func__, Aud_APLL22M_Clk_cntr);
mutex_lock(&auddrv_pmic_mutex);
if (Aud_APLL22M_Clk_cntr == 0)
{
PRINTK_AUDDRV("+%s enable_clock ADC clk(%x)\n", __func__, Aud_APLL22M_Clk_cntr);
#ifdef PM_MANAGER_API
enable_mux(MT_MUX_AUD1, "AUDIO");
clkmux_sel(MT_MUX_AUD1, 1 , "AUDIO"); //select APLL1
if (enable_clock(MT_CG_AUDIO_22M, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
if (enable_clock(MT_CG_AUDIO_APLL_TUNER, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
#endif
}
Aud_APLL22M_Clk_cntr++;
mutex_unlock(&auddrv_pmic_mutex);
}
static int mtk_voice_pm_ops_resume(struct device *device)
{
bool b_modem1_speech_on;
bool b_modem2_speech_on;
AudDrv_Clk_On(); /* should enable clk for access reg */
b_modem1_speech_on = (bool) (Afe_Get_Reg(PCM2_INTF_CON) & 0x1);
b_modem2_speech_on = (bool) (Afe_Get_Reg(PCM_INTF_CON) & 0x1);
AudDrv_Clk_Off();
if (b_modem1_speech_on == true || b_modem2_speech_on == true) {
/* mainpll */
clkmux_sel(MT_CLKMUX_AUD_HF_26M_SEL, MT_CG_SYS_TEMP, "AUDIO ");
clkmux_sel(MT_CLKMUX_AUD_INTBUS_SEL, MT_CG_MPLL_D12, "AUDIO ");
return 0;
}
return 0;
}
/* supend and resume function */
static int mtk_voice_pm_ops_suspend(struct device *device)
{
/* if now in phone call state, not suspend!! */
bool b_modem1_speech_on;
bool b_modem2_speech_on;
AudDrv_Clk_On(); /* should enable clk for access reg */
b_modem1_speech_on = (bool) (Afe_Get_Reg(PCM2_INTF_CON) & 0x1);
b_modem2_speech_on = (bool) (Afe_Get_Reg(PCM_INTF_CON) & 0x1);
AudDrv_Clk_Off(); /* should enable clk for access reg */
pr_warn
("mtk_voice_pm_ops_suspend, b_modem1_speech_on=%d, b_modem2_speech_on=%d, speech_md_usage_control=%d\n",
b_modem1_speech_on, b_modem2_speech_on, speech_md_usage_control);
if (b_modem1_speech_on == true || b_modem2_speech_on == true
|| speech_md_usage_control == true) {
/* select 26M */
clkmux_sel(MT_CLKMUX_AUD_HF_26M_SEL, MT_CG_SYS_26M, "AUDIO ");
clkmux_sel(MT_CLKMUX_AUD_INTBUS_SEL, MT_CG_SYS_26M, "AUDIO ");
return 0;
}
return 0;
}
static void spm_clean_after_wakeup(void)
{
/* disable PCM WDT to stop count if needed */
#if SPM_PCMWDT_EN
spm_write(SPM_PCM_CON1, CON1_CFG_KEY | (spm_read(SPM_PCM_CON1) & ~CON1_PCM_WDT_EN));
#endif
__spm_clean_after_wakeup();
/* restore clock mux: fscp_ck = SYSPLL1_D2 */
clkmux_sel(MT_MUX_SCP, 1, "SPM-Sleep");
}
/* supend and resume function */
static int mtk_voice_md2_bt_pm_ops_suspend(struct device *device)
{
/* if now in phone call state, not suspend!! */
bool b_modem1_speech_on;
bool b_modem2_speech_on;
AudDrv_Clk_On();/* should enable clk for access reg */
b_modem1_speech_on = (bool)(Afe_Get_Reg(PCM2_INTF_CON) & 0x1);
b_modem2_speech_on = (bool)(Afe_Get_Reg(PCM_INTF_CON) & 0x1);
AudDrv_Clk_Off();
if (b_modem1_speech_on == true || b_modem2_speech_on == true) {
clkmux_sel(MT_MUX_AUDINTBUS, 0, "AUDIO"); /* select 26M */
return 0;
}
return 0;
}
static int mtk_voice_md2_bt_pm_ops_resume(struct device *device)
{
bool b_modem1_speech_on;
bool b_modem2_speech_on;
AudDrv_Clk_On();/* should enable clk for access reg */
b_modem1_speech_on = (bool)(Afe_Get_Reg(PCM2_INTF_CON) & 0x1);
b_modem2_speech_on = (bool)(Afe_Get_Reg(PCM_INTF_CON) & 0x1);
AudDrv_Clk_Off();
if (b_modem1_speech_on == true || b_modem2_speech_on == true) {
clkmux_sel(MT_MUX_AUDINTBUS, 1, "AUDIO"); /* mainpll */
return 0;
}
return 0;
}
void disp_bls_init(unsigned int srcWidth, unsigned int srcHeight)
{
struct cust_mt65xx_led *cust_led_list = get_cust_led_list();
struct cust_mt65xx_led *cust = NULL;
struct PWM_config *config_data = NULL;
if(cust_led_list)
{
cust = &cust_led_list[MT65XX_LED_TYPE_LCD];
if((strcmp(cust->name,"lcd-backlight") == 0) && (cust->mode == MT65XX_LED_MODE_CUST_BLS_PWM))
{
config_data = &cust->config_data;
if (config_data->clock_source >= 0 && config_data->clock_source <= 3)
{
unsigned int regVal = DISP_REG_GET(CLK_CFG_1);
clkmux_sel(MT_MUX_PWM, config_data->clock_source, "DISP_PWM");
BLS_DBG("disp_bls_init : CLK_CFG_1 0x%x => 0x%x\n", regVal, DISP_REG_GET(CLK_CFG_1));
}
gPWMDiv = (config_data->div == 0) ? PWM_DEFAULT_DIV_VALUE : config_data->div;
gPWMDiv &= 0x3FF;
BLS_MSG("disp_bls_init : PWM config data (%d,%d)\n", config_data->clock_source, config_data->div);
}
}
BLS_DBG("disp_bls_init : srcWidth = %d, srcHeight = %d\n", srcWidth, srcHeight);
BLS_MSG("disp_bls_init : BLS_EN=0x%x, PWM_DUTY=%d, PWM_DUTY_RD=%d, CG=0x%x, %d, %d\n",
DISP_REG_GET(DISP_REG_BLS_EN),
DISP_REG_GET(DISP_REG_BLS_PWM_DUTY),
DISP_REG_GET(DISP_REG_BLS_PWM_DUTY_RD),
DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON0),
clock_is_on(MT_CG_DISP0_MDP_BLS_26M),
clock_is_on(MT_CG_DISP0_DISP_BLS));
DISP_REG_SET(DISP_REG_BLS_SRC_SIZE, (srcHeight << 16) | srcWidth);
DISP_REG_SET(DISP_REG_BLS_PWM_CON, 0x0 | (gPWMDiv << 16));
DISP_REG_SET(DISP_REG_BLS_BLS_SETTING, 0x0);
DISP_REG_SET(DISP_REG_BLS_INTEN, 0xF);
if (!(DISP_REG_GET(DISP_REG_BLS_EN) & 0x10000))
DISP_REG_SET(DISP_REG_BLS_PWM_DUTY, 0);
disp_bls_update_gamma_lut();
//disp_bls_update_pwm_lut();
disp_bls_config_full(srcWidth, srcHeight);
if (dbg_log)
disp_dump_reg(DISP_MODULE_BLS);
}
//supend and resume function
static int mtk_voice_pm_ops_suspend(struct device *device)
{
// if now in phone call state, not suspend!!
bool b_modem1_speech_on;
bool b_modem2_speech_on;
AudDrv_Clk_On();//should enable clk for access reg
b_modem1_speech_on = (bool)(Afe_Get_Reg(PCM2_INTF_CON) & 0x1);
b_modem2_speech_on = (bool)(Afe_Get_Reg(PCM_INTF_CON) & 0x1);
AudDrv_Clk_Off();//should enable clk for access reg
printk("mtk_voice_pm_ops_suspend, b_modem1_speech_on=%d, b_modem2_speech_on=%d, speech_md_usage_control=%d\n", b_modem1_speech_on, b_modem2_speech_on, speech_md_usage_control);
if (b_modem1_speech_on == true || b_modem2_speech_on == true || speech_md_usage_control == true)
{
clkmux_sel(MT_MUX_AUDINTBUS, 0, "AUDIO"); //select 26M
return 0;
}
return 0;
}
static void spm_clean_after_wakeup(void)
{
/* disable PCM WDT to stop count if needed */
#if SPM_PCMWDT_EN
spm_write(SPM_PCM_CON1, CON1_CFG_KEY | (spm_read(SPM_PCM_CON1) & ~CON1_PCM_WDT_EN));
#endif
#if SPM_PCMTIMER_DIS
spm_write(SPM_PCM_CON1, CON1_CFG_KEY | (spm_read(SPM_PCM_CON1) | CON1_PCM_TIMER_EN));
#endif
__spm_clean_after_wakeup();
//FIXME: for K2 fpga early porting
#if 0
/* restore clock mux: fscp_ck = SYSPLL1_D2 */
clkmux_sel(MT_MUX_SCP, 1, "SPM-Sleep");
#endif
}
static int disp_pwm_config_init(DISP_MODULE_ENUM module, disp_ddp_path_config* pConfig, void* cmdq)
{
struct cust_mt65xx_led *cust_led_list;
struct cust_mt65xx_led *cust;
struct PWM_config *config_data;
unsigned int pwm_div;
disp_pwm_id_t id = (module == DISP_MODULE_PWM0 ? DISP_PWM0 : DISP_PWM1);
unsigned int reg_base = pwm_get_reg_base(id);
int index = index_of_pwm(id);
pwm_div = PWM_DEFAULT_DIV_VALUE;
cust_led_list = get_cust_led_list();
if (cust_led_list)
{
/* WARNING: may overflow if MT65XX_LED_TYPE_LCD not configured properly */
cust = &cust_led_list[MT65XX_LED_TYPE_LCD];
if ((strcmp(cust->name,"lcd-backlight") == 0) && (cust->mode == MT65XX_LED_MODE_CUST_BLS_PWM))
{
config_data = &cust->config_data;
if (config_data->clock_source >= 0 && config_data->clock_source <= 3)
{
unsigned int regVal = DISP_REG_GET(CLK_CFG_1);
clkmux_sel(MT_MUX_PWM, config_data->clock_source, "DISP_PWM");
PWM_MSG("disp_pwm_init : CLK_CFG_1 0x%x => 0x%x", regVal, DISP_REG_GET(CLK_CFG_1));
}
/* Some backlight chip/PMIC(e.g. MT6332) only accept slower clock */
pwm_div = (config_data->div == 0) ? PWM_DEFAULT_DIV_VALUE : config_data->div;
pwm_div &= 0x3FF;
PWM_MSG("disp_pwm_init : PWM config data (%d,%d)", config_data->clock_source, config_data->div);
}
}
atomic_set(&g_pwm_backlight[index], -1);
/* We don't enable PWM until we really need */
DISP_REG_MASK(cmdq, reg_base + DISP_PWM_CON_0_OFF, pwm_div << 16, (0x3ff << 16));
DISP_REG_MASK(cmdq, reg_base + DISP_PWM_CON_1_OFF, 1023, 0x3ff); /* 1024 levels */
/* We don't init the backlight here until AAL/Android give */
return 0;
}
void AudDrv_APLL24M_Clk_Off(void)
{
pr_debug("+%s %d \n", __func__, Aud_APLL24M_Clk_cntr);
mutex_lock(&auddrv_pmic_mutex);
Aud_APLL24M_Clk_cntr--;
if (Aud_APLL24M_Clk_cntr == 0)
{
PRINTK_AUDDRV("+%s disable_clock ADC clk(%x)\n", __func__, Aud_APLL24M_Clk_cntr);
#ifdef PM_MANAGER_API
#if defined(CONFIG_MTK_LEGACY)
if (disable_clock(MT_CG_AUDIO_24M, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
if (disable_clock(MT_CG_AUDIO_APLL2_TUNER, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
#else
if (paudclk->aud_apll24m_clk_status)
{
clk_disable_unprepare(paudclk->aud_apll24m_clk);
}
if (paudclk->aud_apll2_tuner_clk_status)
{
clk_disable_unprepare(paudclk->aud_apll2_tuner_clk);
}
#endif
clkmux_sel(MT_MUX_AUD1, 0, "AUDIO"); //select 26M
disable_mux(MT_MUX_AUD1, "AUDIO");
#endif
}
if (Aud_APLL24M_Clk_cntr < 0)
{
PRINTK_AUDDRV("%s <0 (%d) \n", __func__, Aud_APLL24M_Clk_cntr);
Aud_APLL24M_Clk_cntr = 0;
}
mutex_unlock(&auddrv_pmic_mutex);
}
int mali_platform_power_mode_change(mali_power_mode power_mode)
{
unsigned long flags;
switch (power_mode)
{
case MALI_POWER_MODE_ON:
MALI_DEBUG_PRINT(3, ("Mali platform: Got MALI_POWER_MODE_ON event, %s\n",
atomic_read((atomic_t *)&bPoweroff) ? "powering on" : "already on"));
if (atomic_read((atomic_t *)&bPoweroff) == 1)
{
MALI_DEBUG_PRINT(2,("[+]MFG enable_clock \n"));
mfg_pwr_lock(flags);
if (!clock_is_on(MT_CG_MFG_PDN_BG3D_SW_CG))
{
enable_clock(MT_CG_MFG_PDN_BG3D_SW_CG, "G3D_DRV");
/// enable WHPLL and set the GPU freq. to 500MHz
if(get_gpu_level() != GPU_LEVEL_0){
clkmux_sel(MT_CLKMUX_MFG_MUX_SEL, MT_CG_GPU_500P5M_EN, "G3D_DRV");
}
}
mfg_pwr_unlock(flags);
MALI_DEBUG_PRINT(2,("[-]MFG enable_clock \n"));
#if defined(CONFIG_MALI400_PROFILING)
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
MALI_PROFILING_EVENT_CHANNEL_GPU |
MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE, 500,
1200/1000, 0, 0, 0);
#endif
atomic_set((atomic_t *)&bPoweroff, 0);
}
break;
case MALI_POWER_MODE_LIGHT_SLEEP:
case MALI_POWER_MODE_DEEP_SLEEP:
MALI_DEBUG_PRINT(1, ("Mali platform: Got %s event, %s\n", power_mode ==
MALI_POWER_MODE_LIGHT_SLEEP ? "MALI_POWER_MODE_LIGHT_SLEEP" :
"MALI_POWER_MODE_DEEP_SLEEP", atomic_read((atomic_t *)&bPoweroff) ? "already off" : "powering off"));
if (atomic_read((atomic_t *)&bPoweroff) == 0)
{
MALI_DEBUG_PRINT(2,("[+]MFG disable_clock \n"));
mfg_pwr_lock(flags);
if (clock_is_on(MT_CG_MFG_PDN_BG3D_SW_CG))
{
disable_clock(MT_CG_MFG_PDN_BG3D_SW_CG, "G3D_DRV");
}
mfg_pwr_unlock(flags);
MALI_DEBUG_PRINT(2,("[-]MFG disable_clock \n"));
#if defined(CONFIG_MALI400_PROFILING)
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
MALI_PROFILING_EVENT_CHANNEL_GPU |
MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE, 0, 0, 0, 0, 0);
#endif
atomic_set((atomic_t *)&bPoweroff, 1);
}
break;
}
}
void mali_platform_power_mode_change(mali_power_mode power_mode)
{
#if 0
unsigned long flags;
switch (power_mode)
{
case MALI_POWER_MODE_ON:
MALI_DEBUG_PRINT(3, ("Mali platform: Got MALI_POWER_MODE_ON event, %s\n",
atomic_read((atomic_t *)&bPoweroff) ? "powering on" : "already on"));
if (atomic_read((atomic_t *)&bPoweroff) == 1)
{
MALI_DEBUG_PRINT(3,("[+]MFG enable_clock \n"));
mfg_pwr_lock(flags);
//trace_printk("[GPU power] MFG ON\n");
if (!clock_is_on(MT_CG_MFG_G3D))
{
if(_need_univpll) {
enable_pll_spec(UNIVPLL, "GPU");
}
enable_clock(MT_CG_DISP0_SMI_COMMON, "MFG");
enable_clock(MT_CG_MFG_G3D, "MFG");
if(_need_univpll) {
clkmux_sel(MT_MUX_MFG, 6, "GPU");
}
}
mfg_pwr_unlock(flags);
MALI_DEBUG_PRINT(3,("[-]MFG enable_clock \n"));
#if defined(CONFIG_MALI400_PROFILING)
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
MALI_PROFILING_EVENT_CHANNEL_GPU |
MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE, 500,
1200/1000, 0, 0, 0);
#endif
atomic_set((atomic_t *)&bPoweroff, 0);
}
break;
case MALI_POWER_MODE_LIGHT_SLEEP:
case MALI_POWER_MODE_DEEP_SLEEP:
MALI_DEBUG_PRINT(3, ("Mali platform: Got %s event, %s\n", power_mode ==
MALI_POWER_MODE_LIGHT_SLEEP ? "MALI_POWER_MODE_LIGHT_SLEEP" :
"MALI_POWER_MODE_DEEP_SLEEP", atomic_read((atomic_t *)&bPoweroff) ? "already off" : "powering off"));
if (atomic_read((atomic_t *)&bPoweroff) == 0)
{
MALI_DEBUG_PRINT(3,("[+]MFG disable_clock \n"));
mfg_pwr_lock(flags);
//trace_printk("[GPU power] MFG OFF\n");
if (clock_is_on(MT_CG_MFG_G3D))
{
disable_clock(MT_CG_MFG_G3D, "MFG");
disable_clock(MT_CG_DISP0_SMI_COMMON, "MFG");
if(_need_univpll) {
disable_pll_spec(UNIVPLL, "GPU");
}
}
mfg_pwr_unlock(flags);
MALI_DEBUG_PRINT(3,("[-]MFG disable_clock \n"));
#if defined(CONFIG_MALI400_PROFILING)
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE |
MALI_PROFILING_EVENT_CHANNEL_GPU |
MALI_PROFILING_EVENT_REASON_SINGLE_GPU_FREQ_VOLT_CHANGE, 0, 0, 0, 0, 0);
#endif
atomic_set((atomic_t *)&bPoweroff, 1);
}
break;
}
#endif
}
int disp_bls_config(void)
{
#if !defined(CONFIG_MTK_AAL_SUPPORT)
struct cust_mt65xx_led *cust_led_list = get_cust_led_list();
struct cust_mt65xx_led *cust = NULL;
struct PWM_config *config_data = NULL;
if(cust_led_list)
{
cust = &cust_led_list[MT65XX_LED_TYPE_LCD];
if((strcmp(cust->name,"lcd-backlight") == 0) && (cust->mode == MT65XX_LED_MODE_CUST_BLS_PWM))
{
config_data = &cust->config_data;
if (config_data->clock_source >= 0 && config_data->clock_source <= 3)
{
unsigned int regVal = DISP_REG_GET(CLK_CFG_1);
clkmux_sel(MT_MUX_PWM, config_data->clock_source, "DISP_PWM");
BLS_DBG("disp_bls_init : CLK_CFG_1 0x%x => 0x%x\n", regVal, DISP_REG_GET(CLK_CFG_1));
}
gPWMDiv = (config_data->div == 0) ? PWM_DEFAULT_DIV_VALUE : config_data->div;
gPWMDiv &= 0x3FF;
BLS_MSG("disp_bls_config : PWM config data (%d,%d)\n", config_data->clock_source, config_data->div);
}
}
if (!clock_is_on(MT_CG_DISP0_MDP_BLS_26M) || !gBLSPowerOn)
{
BLS_MSG("disp_bls_config: enable clock\n");
enable_clock(MT_CG_DISP0_SMI_LARB0, "DDP");
enable_clock(MT_CG_DISP0_MDP_BLS_26M , "DDP");
gBLSPowerOn = 1;
}
BLS_MSG("disp_bls_config : BLS_EN=0x%x, PWM_DUTY=%d, PWM_DUTY_RD=%d, CG=0x%x, %d, %d\n",
DISP_REG_GET(DISP_REG_BLS_EN),
DISP_REG_GET(DISP_REG_BLS_PWM_DUTY),
DISP_REG_GET(DISP_REG_BLS_PWM_DUTY_RD),
DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON0),
clock_is_on(MT_CG_DISP0_MDP_BLS_26M),
clock_is_on(MT_CG_DISP0_DISP_BLS));
#ifdef USE_DISP_BLS_MUTEX
BLS_MSG("disp_bls_config : gBLSMutexID = %d\n", gBLSMutexID);
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_RST(gBLSMutexID), 1);
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_RST(gBLSMutexID), 0);
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_MOD(gBLSMutexID), 0x200); // BLS
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_SOF(gBLSMutexID), 0); // single mode
DISP_REG_SET(DISP_REG_CONFIG_MUTEX_EN(gBLSMutexID), 1);
if (disp_bls_get_mutex() == 0)
{
#else
BLS_MSG("disp_bls_config\n");
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x3);
#endif
if (!(DISP_REG_GET(DISP_REG_BLS_EN) & 0x10000))
DISP_REG_SET(DISP_REG_BLS_PWM_DUTY, 0);
DISP_REG_SET(DISP_REG_BLS_PWM_CON, 0x0 | (gPWMDiv << 16));
//DISP_REG_SET(DISP_REG_BLS_EN, 0x00010001); //Enable BLS_EN
#ifdef USE_DISP_BLS_MUTEX
if (disp_bls_release_mutex() == 0)
return 0;
}
return -1;
#else
DISP_REG_SET(DISP_REG_BLS_DEBUG, 0x0);
#endif
#endif
BLS_MSG("disp_bls_config:-\n");
return 0;
}
void AudDrv_Suspend_Clk_Off(void)
{
unsigned long flags;
spin_lock_irqsave(&auddrv_Clk_lock, flags);
if (Aud_Core_Clk_cntr > 0)
{
#ifdef PM_MANAGER_API
if (Aud_AFE_Clk_cntr > 0)
{
#if defined(CONFIG_MTK_LEGACY)
if (disable_clock(MT_CG_AUDIO_AFE, "AUDIO"))
{
printk("Aud enable_clock MT_CG_AUDIO_AFE fail !!!\n");
}
#else
if (paudclk->aud_afe_clk_status)
{
clk_disable_unprepare(paudclk->aud_afe_clk);
}
#endif
}
if (Aud_I2S_Clk_cntr > 0)
{
#if defined(CONFIG_MTK_LEGACY)
if (disable_clock(MT_CG_AUDIO_I2S, "AUDIO"))
{
PRINTK_AUD_ERROR("disable_clock MT_CG_AUDIO_I2S fail");
}
#else
if (paudclk->aud_i2s_clk_status)
{
clk_disable_unprepare(paudclk->aud_i2s_clk);
}
#endif
}
if (Aud_ADC_Clk_cntr > 0)
{
Afe_Set_Reg(AUDIO_TOP_CON0, 1 << 24 , 1 << 24);
}
if (Aud_ADC2_Clk_cntr > 0)
{
#if 0 //K2 removed
if (disable_clock(MT_CG_AUDIO_ADDA2, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
#endif
}
if (Aud_ADC3_Clk_cntr > 0)
{
#if 0 //K2 removed
if (disable_clock(MT_CG_AUDIO_ADDA3, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
#endif
}
if (Aud_ANA_Clk_cntr > 0)
{
}
if (Aud_HDMI_Clk_cntr > 0)
{
}
if (Aud_APLL22M_Clk_cntr > 0)
{
#if defined(CONFIG_MTK_LEGACY)
if (disable_clock(MT_CG_AUDIO_22M, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
if (disable_clock(MT_CG_AUDIO_APLL_TUNER, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
#else
if (paudclk->aud_apll22m_clk_status)
{
clk_disable_unprepare(paudclk->aud_apll22m_clk);
}
if (paudclk->aud_apll1_tuner_clk_status)
{
clk_disable_unprepare(paudclk->aud_apll1_tuner_clk);
}
#endif
clkmux_sel(MT_MUX_AUD1, 0, "AUDIO"); //select 26M
disable_mux(MT_MUX_AUD1, "AUDIO");
}
if (Aud_APLL24M_Clk_cntr > 0)
{
#if defined(CONFIG_MTK_LEGACY)
if (disable_clock(MT_CG_AUDIO_24M, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
if (disable_clock(MT_CG_AUDIO_APLL2_TUNER, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
clkmux_sel(MT_MUX_AUD2, 0, "AUDIO"); //select 26M
disable_mux(MT_MUX_AUD2, "AUDIO");
#else
if (paudclk->aud_apll24m_clk_status)
{
clk_disable_unprepare(paudclk->aud_apll24m_clk);
}
if (paudclk->aud_apll2_tuner_clk_status)
{
clk_disable_unprepare(paudclk->aud_apll2_tuner_clk);
}
#endif
}
#endif
}
spin_unlock_irqrestore(&auddrv_Clk_lock, flags);
}
void AudDrv_Suspend_Clk_On(void)
{
unsigned long flags;
#if !defined(CONFIG_MTK_LEGACY)
int ret = 0;
#endif
spin_lock_irqsave(&auddrv_Clk_lock, flags);
if (Aud_Core_Clk_cntr > 0)
{
#ifdef PM_MANAGER_API
#if defined(CONFIG_MTK_LEGACY)
if (enable_clock(MT_CG_AUDIO_AFE, "AUDIO"))
{
PRINTK_AUD_ERROR("Aud enable_clock MT_CG_AUDIO_AFE fail !!!\n");
}
#else
if (paudclk->aud_afe_clk_status)
{
ret = clk_prepare_enable(paudclk->aud_afe_clk);
if (!ret)
{
pr_err("%s Aud enable_clock enable_clock aud_afe_clk fail", __func__);
BUG();
return;
}
}
else
{
pr_err("%s clk_status error Aud enable_clock aud_afe_clk fail", __func__);
BUG();
return;
}
#endif
if (Aud_I2S_Clk_cntr > 0)
{
#if defined(CONFIG_MTK_LEGACY)
if (enable_clock(MT_CG_AUDIO_I2S, "AUDIO"))
{
PRINTK_AUD_ERROR("enable_clock MT_CG_AUDIO_I2S fail");
}
#else
if (paudclk->aud_i2s_clk_status)
{
ret = clk_prepare_enable(paudclk->aud_i2s_clk);
if (!ret)
{
pr_err("%s Aud enable_clock enable_clock aud_i2s_clk fail", __func__);
BUG();
return;
}
}
else
{
pr_err("%s clk_status error Aud enable_clock aud_i2s_clk fail", __func__);
BUG();
return;
}
#endif
}
if (Aud_ADC_Clk_cntr > 0)
{
Afe_Set_Reg(AUDIO_TOP_CON0, 0 << 24 , 1 << 24);
}
if (Aud_ADC2_Clk_cntr > 0)
{
#if 0 //K2 removed
if (enable_clock(MT_CG_AUDIO_ADDA2, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
#endif
}
if (Aud_ADC3_Clk_cntr > 0)
{
#if 0 //K2 removed
if (enable_clock(MT_CG_AUDIO_ADDA3, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
#endif
}
if (Aud_ANA_Clk_cntr > 0)
{
}
if (Aud_HDMI_Clk_cntr > 0)
{
}
if (Aud_APLL22M_Clk_cntr > 0)
{
enable_mux(MT_MUX_AUD1, "AUDIO");
clkmux_sel(MT_MUX_AUD1, 1 , "AUDIO"); //select APLL1
#if defined(CONFIG_MTK_LEGACY)
if (enable_clock(MT_CG_AUDIO_22M, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
if (enable_clock(MT_CG_AUDIO_APLL_TUNER, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
#else
if (paudclk->aud_apll22m_clk_status)
{
ret = clk_prepare_enable(paudclk->aud_apll22m_clk);
if (!ret)
{
pr_err("%s Aud enable_clock enable_clock aud_apll22m_clk fail", __func__);
BUG();
return;
}
}
else
{
pr_err("%s clk_status error Aud enable_clock aud_apll22m_clk fail", __func__);
BUG();
return;
}
if (paudclk->aud_apll1_tuner_clk_status)
{
ret = clk_prepare_enable(paudclk->aud_apll1_tuner_clk);
if (!ret)
{
pr_err("%s Aud enable_clock enable_clock aud_apll1_tuner_clk fail", __func__);
BUG();
return;
}
}
else
{
pr_err("%s clk_status error Aud enable_clock aud_apll1_tuner_clk fail", __func__);
BUG();
return;
}
#endif
}
if (Aud_APLL24M_Clk_cntr > 0)
{
enable_mux(MT_MUX_AUD2, "AUDIO");
clkmux_sel(MT_MUX_AUD2, 1, "AUDIO"); //APLL2
#if defined(CONFIG_MTK_LEGACY)
if (enable_clock(MT_CG_AUDIO_24M, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
if (enable_clock(MT_CG_AUDIO_APLL2_TUNER, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
#else
if (paudclk->aud_apll24m_clk_status)
{
ret = clk_prepare_enable(paudclk->aud_apll24m_clk);
if (!ret)
{
pr_err("%s Aud enable_clock enable_clock aud_apll24m_clk fail", __func__);
BUG();
return;
}
}
else
{
pr_err("%s clk_status error Aud enable_clock aud_apll24m_clk fail", __func__);
BUG();
return;
}
if (paudclk->aud_apll2_tuner_clk_status)
{
ret = clk_prepare_enable(paudclk->aud_apll2_tuner_clk);
if (!ret)
{
pr_err("%s Aud enable_clock enable_clock aud_apll2_tuner_clk fail", __func__);
BUG();
return;
}
}
else
{
pr_err("%s clk_status error Aud enable_clock aud_apll2_tuner_clk fail", __func__);
BUG();
return;
}
#endif
}
#endif
}
spin_unlock_irqrestore(&auddrv_Clk_lock, flags);
}
void AudDrv_APLL22M_Clk_On(void)
{
pr_debug("+%s %d \n", __func__, Aud_APLL22M_Clk_cntr);
#if !defined(CONFIG_MTK_LEGACY)
int ret = 0;
#endif
mutex_lock(&auddrv_pmic_mutex);
if (Aud_APLL22M_Clk_cntr == 0)
{
PRINTK_AUDDRV("+%s enable_clock ADC clk(%x)\n", __func__, Aud_APLL22M_Clk_cntr);
#ifdef PM_MANAGER_API
pr_debug("+%s enable_mux ADC \n", __func__);
enable_mux(MT_MUX_AUD1, "AUDIO");//MT_MUX_AUD1 CLK_CFG_6 => [7]: pdn_aud_1 [15]: ,MT_MUX_AUD2: pdn_aud_2
clkmux_sel(MT_MUX_AUD1, 1 , "AUDIO"); //select APLL1 ,hf_faud_1_ck is mux of 26M and APLL1_CK
pll_fsel(APLL1, 0xb7945ea6); //APLL1 90.3168M
//pdn_aud_1 => power down hf_faud_1_ck, hf_faud_1_ck is mux of 26M and APLL1_CK
//pdn_aud_2 => power down hf_faud_2_ck, hf_faud_2_ck is mux of 26M and APLL2_CK (D1 is WHPLL)
#if defined(CONFIG_MTK_LEGACY)
if (enable_clock(MT_CG_AUDIO_22M, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
if (enable_clock(MT_CG_AUDIO_APLL_TUNER, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
#else
if (paudclk->aud_apll22m_clk_status)
{
ret = clk_prepare_enable(paudclk->aud_apll22m_clk);
if (!ret)
{
pr_err("%s Aud enable_clock enable_clock aud_apll22m_clk fail", __func__);
BUG();
return;
}
}
else
{
pr_err("%s clk_status error Aud enable_clock aud_apll22m_clk fail", __func__);
BUG();
return;
}
if (paudclk->aud_apll1_tuner_clk_status)
{
ret = clk_prepare_enable(paudclk->aud_apll1_tuner_clk);
if (!ret)
{
pr_err("%s Aud enable_clock enable_clock aud_apll1_tuner_clk fail", __func__);
BUG();
return;
}
}
else
{
pr_err("%s clk_status error Aud enable_clock aud_apll1_tuner_clk fail", __func__);
BUG();
return;
}
#endif
#endif
}
Aud_APLL22M_Clk_cntr++;
mutex_unlock(&auddrv_pmic_mutex);
}
void AudDrv_APLL24M_Clk_On(void)
{
pr_debug("+%s %d \n", __func__, Aud_APLL24M_Clk_cntr);
#if !defined(CONFIG_MTK_LEGACY)
int ret = 0;
#endif
mutex_lock(&auddrv_pmic_mutex);
if (Aud_APLL24M_Clk_cntr == 0)
{
PRINTK_AUDDRV("+%s enable_clock ADC clk(%x)\n", __func__, Aud_APLL24M_Clk_cntr);
#ifdef PM_MANAGER_API
enable_mux(MT_MUX_AUD1, "AUDIO");
clkmux_sel(MT_MUX_AUD1, 1, "AUDIO"); //hf_faud_1_ck apll1_ck
pll_fsel(APLL1, 0xbc7ea932); //ALPP1 98.304M
#if defined(CONFIG_MTK_LEGACY)
if (enable_clock(MT_CG_AUDIO_24M, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
if (enable_clock(MT_CG_AUDIO_APLL2_TUNER, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
#else
if (paudclk->aud_apll24m_clk_status)
{
ret = clk_prepare_enable(paudclk->aud_apll24m_clk);
if (!ret)
{
pr_err("%s Aud enable_clock enable_clock aud_apll24m_clk fail", __func__);
BUG();
return;
}
}
else
{
pr_err("%s clk_status error Aud enable_clock aud_apll24m_clk fail", __func__);
BUG();
return;
}
if (paudclk->aud_apll2_tuner_clk_status)
{
ret = clk_prepare_enable(paudclk->aud_apll2_tuner_clk);
if (!ret)
{
pr_err("%s Aud enable_clock enable_clock aud_apll2_tuner_clk fail", __func__);
BUG();
return;
}
}
else
{
pr_err("%s clk_status error Aud enable_clock aud_apll2_tuner_clk fail", __func__);
BUG();
return;
}
#endif
#endif
}
Aud_APLL24M_Clk_cntr++;
mutex_unlock(&auddrv_pmic_mutex);
}
void AudDrv_Suspend_Clk_On(void)
{
unsigned long flags;
spin_lock_irqsave(&auddrv_Clk_lock, flags);
if (Aud_Core_Clk_cntr > 0)
{
#ifdef PM_MANAGER_API
if (Aud_AFE_Clk_cntr > 0)
{
if (enable_clock(MT_CG_AUDIO_AFE, "AUDIO"))
{
xlog_printk(ANDROID_LOG_ERROR, "Sound", "Aud enable_clock MT_CG_AUDIO_AFE fail !!!\n");
}
}
if (Aud_I2S_Clk_cntr > 0)
{
if (enable_clock(MT_CG_AUDIO_I2S, "AUDIO"))
{
PRINTK_AUD_ERROR("enable_clock MT_CG_AUDIO_I2S fail");
}
}
if (Aud_ADC_Clk_cntr > 0)
{
Afe_Set_Reg(AUDIO_TOP_CON0, 0 << 24 , 1 << 24);
}
if (Aud_ADC2_Clk_cntr > 0)
{
#if 0 //K2 removed
if (enable_clock(MT_CG_AUDIO_ADDA2, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
#endif
}
if (Aud_ADC3_Clk_cntr > 0)
{
#if 0 //K2 removed
if (enable_clock(MT_CG_AUDIO_ADDA3, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
#endif
}
if (Aud_ANA_Clk_cntr > 0)
{
}
if (Aud_HDMI_Clk_cntr > 0)
{
}
if (Aud_APLL22M_Clk_cntr > 0)
{
enable_mux(MT_MUX_AUD1, "AUDIO");
clkmux_sel(MT_MUX_AUD1, 1 , "AUDIO"); //select APLL1
if (enable_clock(MT_CG_AUDIO_22M, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
if (enable_clock(MT_CG_AUDIO_APLL_TUNER, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
}
if (Aud_APLL24M_Clk_cntr > 0)
{
enable_mux(MT_MUX_AUD2, "AUDIO");
clkmux_sel(MT_MUX_AUD2, 1, "AUDIO"); //APLL2
if (enable_clock(MT_CG_AUDIO_24M, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
if (enable_clock(MT_CG_AUDIO_APLL2_TUNER, "AUDIO"))
{
PRINTK_AUD_CLK("%s fail", __func__);
}
}
#endif
}
spin_unlock_irqrestore(&auddrv_Clk_lock, flags);
}
