/*
* Routine: clock_init_uart
* Description: init the PLL and clock for the UART(s)
*/
static void clock_init_uart(void)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
struct clk_pll *pll = &clkrst->crc_pll[CLOCK_PLL_ID_PERIPH];
u32 reg;
reg = readl(&pll->pll_base);
if (!(reg & PLL_BASE_OVRRIDE_MASK)) {
/* Override pllp setup for 216MHz operation. */
reg = PLL_BYPASS_MASK | PLL_BASE_OVRRIDE_MASK |
(1 << PLL_DIVP_SHIFT) | (0xc << PLL_DIVM_SHIFT);
reg |= (NVRM_PLLP_FIXED_FREQ_KHZ / 500) << PLL_DIVN_SHIFT;
writel(reg, &pll->pll_base);
reg |= PLL_ENABLE_MASK;
writel(reg, &pll->pll_base);
reg &= ~PLL_BYPASS_MASK;
writel(reg, &pll->pll_base);
}
#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
/* Assert UART reset and enable clock */
reset_set_enable(PERIPH_ID_UART1, 1);
clock_enable(PERIPH_ID_UART1);
/* Enable pllp_out0 to UART */
reg = readl(&clkrst->crc_clk_src_uarta);
reg &= 0x3FFFFFFF; /* UARTA_CLK_SRC = 00, PLLP_OUT0 */
writel(reg, &clkrst->crc_clk_src_uarta);
/* wait for 2us */
udelay(2);
/* De-assert reset to UART */
reset_set_enable(PERIPH_ID_UART1, 0);
#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
/* Assert UART reset and enable clock */
reset_set_enable(PERIPH_ID_UART4, 1);
clock_enable(PERIPH_ID_UART4);
/* Enable pllp_out0 to UART */
reg = readl(&clkrst->crc_clk_src_uartd);
reg &= 0x3FFFFFFF; /* UARTD_CLK_SRC = 00, PLLP_OUT0 */
writel(reg, &clkrst->crc_clk_src_uartd);
/* wait for 2us */
udelay(2);
/* De-assert reset to UART */
reset_set_enable(PERIPH_ID_UART4, 0);
#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
}
void mddi_clock_init(unsigned num, unsigned rate)
{
unsigned clock_id;
if (num == 0)
clock_id = PMDH_CLK;
else
clock_id = EMDH_CLK;
clock_enable(clock_id);
clock_set_rate(clock_id, rate);
#ifdef PLATFORM_MSM7X30
clock_enable(PMDH_P_CLK);
#endif
}
/*
* 初始化SPI寄存器
* */
static void spi_init(void)
{
#ifdef _DEBUG_GM814X
printk(KERN_INFO "2-----spi_init------\n");
#endif
gpio_select();
clock_enable();
spi_reset();
// 1. SET CH_CFG
CH_CFG = HIGH_SPEED_EN | SW_RST | MASTER | CPOL | CPHA;
// 2. SET CLK_CFG
CLK_CFG &= ~ ( 0x7ff );
CLK_CFG = SPI_CLKSEL | ENCLK | SPI_SCALER;
// 3. SET MODE_CFG
MODE_CFG &= ( u32 ) ( 1 << 31 );
MODE_CFG = CH_WIDTH | TRAILING_CNT | BUS_WIDTH | RX_RDY_LVL | TX_RDY_LVL | RX_DMA_SW | TX_DMA_SW | DMA_TYPE;
// 4. SET SLAVE_SEL
SLAVE_SEL = SLAVE_CS_HIGH |SLAVE_AUTO_OFF;
// 5. SET SPI_INT_EN
SPI_INT_EN = SPI_INT_ENABLE;
// 6. SET SWAP_CONFIG
SWAP_CONFIG = RX_SWAP_EN | RX_SWAP_MODE | TX_SWAP_EN | TX_SWAP_MODE;
#ifdef _DEBUG_GM814X
printk(KERN_INFO "2------spi_init end---------\n");
#endif
}
static void enable_sor_periph_clocks(void)
{
clock_enable(CLK_L_HOST1X, 0, 0, 0, 0, CLK_X_DPAUX, 0);
/* Give clocks time to stabilize. */
udelay(IO_STABILIZATION_DELAY);
}
/*
* We need to take ALL audio devices conntected to AHUB (AUDIO, APBIF,
* I2S, DAM, AMX, ADX, SPDIF, AFC) out of reset and enable the clocks.
* Otherwise reading AHUB devices will hang when the kernel boots.
*/
static void enable_required_clocks(void)
{
static enum periph_id ids[] = {
PERIPH_ID_I2S0,
PERIPH_ID_I2S1,
PERIPH_ID_I2S2,
PERIPH_ID_I2S3,
PERIPH_ID_I2S4,
PERIPH_ID_AUDIO,
PERIPH_ID_APBIF,
PERIPH_ID_DAM0,
PERIPH_ID_DAM1,
PERIPH_ID_DAM2,
PERIPH_ID_AMX0,
PERIPH_ID_AMX1,
PERIPH_ID_ADX0,
PERIPH_ID_ADX1,
PERIPH_ID_SPDIF,
PERIPH_ID_AFC0,
PERIPH_ID_AFC1,
PERIPH_ID_AFC2,
PERIPH_ID_AFC3,
PERIPH_ID_AFC4,
PERIPH_ID_AFC5,
PERIPH_ID_EXTPERIPH1
};
int i;
for (i = 0; i < ARRAY_SIZE(ids); i++)
clock_enable(ids[i]);
udelay(2);
for (i = 0; i < ARRAY_SIZE(ids); i++)
reset_set_enable(ids[i], 0);
}
/*
* Configure PORT_1C as data with PORT_1D as the valid signal. Test receiving
* two different words of data and check they are the correct values.
*/
void port_test_input(chanend c)
{
port p = port_enable(XS1_PORT_1C);
port_set_buffered(p);
port_set_transfer_width(p, 32);
port p_ready = port_enable(XS1_PORT_1D);
clock clk = clock_enable(XS1_CLKBLK_2);
clock_start(clk);
port_configure_in_strobed_slave(p, p_ready, clk);
chan_output_word(c, 0); // Send ack
unsigned int x = port_input(p);
if (x != 0xfeedbeef) {
debug_printf("Error %x received instead of 0xfeedbeef\n", x);
}
x = port_input(p);
if (x != 0x12345678) {
debug_printf("Error %x received instead of 0x12345678\n", x);
}
chan_output_word(c, 0); // Send ack
port_disable(p);
port_disable(p_ready);
clock_disable(clk);
// Get information about the tile/core running the server for debug messages
unsigned tile_id = get_local_tile_id();
unsigned core_id = get_logical_core_id();
debug_printf("%x:%d: input done\n", tile_id, core_id);
}
/** Low level init function.
*/
int __low_level_init(void) {
wdt_disable();
pll_init();
clock_enable();
return 1;
}
/*
* Configure PORT_1A as data with PORT_1B as the valid signal. Ensure that the
* receiver is ready using a channel end. Send a word of data, delay for a while
* and send another word to ensure the valid signals are functioning.
*/
void port_test_output(chanend c)
{
port p = port_enable(XS1_PORT_1A);
port_set_buffered(p);
port_set_transfer_width(p, 32);
port p_ready = port_enable(XS1_PORT_1B);
clock clk = clock_enable(XS1_CLKBLK_1);
clock_start(clk);
port_configure_out_strobed_master(p, p_ready, clk, 0);
chan_input_word(c); // Wait for ack
port_output(p, 0xfeedbeef);
timer tmr = timer_alloc();
timer_delay(tmr, 1000);
timer_free(tmr);
port_output(p, 0x12345678);
chan_input_word(c); // Wait for ack
port_disable(p);
port_disable(p_ready);
clock_disable(clk);
// Get information about the tile/core running the server for debug messages
unsigned tile_id = get_local_tile_id();
unsigned core_id = get_logical_core_id();
debug_printf("%x:%d: output done\n", tile_id, core_id);
}
int mmc_clock_enable_disable(unsigned id, unsigned enable)
{
if (enable) {
return clock_enable(id); //Enable mmc clock rate
} else {
return clock_disable(id); //Disable mmc clock rate
}
}
void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w, u32 x)
{
clock_enable(l, h, u, v, w, x);
/* Give clocks time to stabilize. */
udelay(IO_STABILIZATION_DELAY);
clock_clr_reset(l, h, u, v, w, x);
}
static int tegra_car_clk_enable(struct clk *clk)
{
debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
clk->id);
clock_enable(clk->id);
return 0;
}
void nx_hwinit()
{
enable_clocks();
clock_enable_se();
clock_enable_fuse(1);
fuse_disable_program();
mc_enable();
config_oscillators();
_REG(0x70000000, 0x40) = 0;
config_gpios();
clock_enable_i2c(I2C_1);
clock_enable_i2c(I2C_5);
clock_enable(&clock_unk1);
clock_enable(&clock_unk2);
i2c_init(I2C_1);
i2c_init(I2C_5);
//Config PMIC (TODO: use max77620.h)
i2c_send_byte(I2C_5, 0x3C, 4, 0x40);
i2c_send_byte(I2C_5, 0x3C, 0x41, 0x78);
i2c_send_byte(I2C_5, 0x3C, 0x43, 0x38);
i2c_send_byte(I2C_5, 0x3C, 0x44, 0x3A);
i2c_send_byte(I2C_5, 0x3C, 0x45, 0x38);
i2c_send_byte(I2C_5, 0x3C, 0x4A, 0xF);
i2c_send_byte(I2C_5, 0x3C, 0x4E, 0xC7);
i2c_send_byte(I2C_5, 0x3C, 0x4F, 0x4F);
i2c_send_byte(I2C_5, 0x3C, 0x50, 0x29);
i2c_send_byte(I2C_5, 0x3C, 0x52, 0x1B);
i2c_send_byte(I2C_5, 0x3C, 0x16, 42); //42 = (1000 * 1125 - 600000) / 12500
config_pmc_scratch();
CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & 0xFFFF8888 | 0x3333;
mc_config_carveout();
sdram_init();
}
static void enable_cpu_clocks(void)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 reg;
debug("enable_cpu_clocks entry\n");
/* Wait for PLL-X to lock */
do {
reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
} while ((reg & (1 << 27)) == 0);
/* Wait until all clocks are stable */
udelay(PLL_STABILIZATION_DELAY);
writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
/* Always enable the main CPU complex clocks */
clock_enable(PERIPH_ID_CPU);
clock_enable(PERIPH_ID_CPULP);
clock_enable(PERIPH_ID_CPUG);
}
/*
* Routine: clock_init_mmc
* Description: init the PLL and clocks for the SDMMC controllers
*/
static void clock_init_mmc(void)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 reg;
/* Do the SDMMC resets/clock enables */
reset_set_enable(PERIPH_ID_SDMMC4, 1);
clock_enable(PERIPH_ID_SDMMC4);
/* Enable pllp_out0 to SDMMC4 */
reg = readl(&clkrst->crc_clk_src_sdmmc4);
reg &= 0x3FFFFF00; /* SDMMC4_CLK_SRC = 00, PLLP_OUT0 */
reg |= (10 << 1); /* n-1, 11-1 shl 1 */
writel(reg, &clkrst->crc_clk_src_sdmmc4);
/*
* As per the Tegra2 TRM, section 5.3.4:
* 'Wait 2 us for the clock to flush through the pipe/logic'
*/
udelay(2);
reset_set_enable(PERIPH_ID_SDMMC4, 1);
reset_set_enable(PERIPH_ID_SDMMC3, 1);
clock_enable(PERIPH_ID_SDMMC3);
/* Enable pllp_out0 to SDMMC4, set divisor to 11 for 20MHz */
reg = readl(&clkrst->crc_clk_src_sdmmc3);
reg &= 0x3FFFFF00; /* SDMMC3_CLK_SRC = 00, PLLP_OUT0 */
reg |= (10 << 1); /* n-1, 11-1 shl 1 */
writel(reg, &clkrst->crc_clk_src_sdmmc3);
/* wait for 2us */
udelay(2);
reset_set_enable(PERIPH_ID_SDMMC3, 0);
}
static void enable_cpu_clocks(void)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU];
u32 reg;
debug("%s entry\n", __func__);
/* Wait for PLL-X to lock */
do {
reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
debug("%s: PLLX base = 0x%08X\n", __func__, reg);
} while ((reg & (1 << pllinfo->lock_det)) == 0);
debug("%s: PLLX locked, delay for stable clocks\n", __func__);
/* Wait until all clocks are stable */
udelay(PLL_STABILIZATION_DELAY);
debug("%s: Setting CCLK_BURST and DIVIDER\n", __func__);
writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
debug("%s: Enabling clock to all CPUs\n", __func__);
/* Enable the clock to all CPUs */
reg = CLR_CPU3_CLK_STP | CLR_CPU2_CLK_STP | CLR_CPU1_CLK_STP |
CLR_CPU0_CLK_STP;
writel(reg, &clkrst->crc_clk_cpu_cmplx_clr);
debug("%s: Enabling main CPU complex clocks\n", __func__);
/* Always enable the main CPU complex clocks */
clock_enable(PERIPH_ID_CPU);
clock_enable(PERIPH_ID_CPULP);
clock_enable(PERIPH_ID_CPUG);
debug("%s: Done\n", __func__);
}
static int tegra124_lcd_init(struct udevice *dev, void *lcdbase,
enum video_log2_bpp l2bpp)
{
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct display_timing timing;
int ret;
clock_set_up_plldp();
clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 408000000);
clock_enable(PERIPH_ID_HOST1X);
clock_enable(PERIPH_ID_DISP1);
clock_enable(PERIPH_ID_PWM);
clock_enable(PERIPH_ID_DPAUX);
clock_enable(PERIPH_ID_SOR0);
udelay(2);
reset_set_enable(PERIPH_ID_HOST1X, 0);
reset_set_enable(PERIPH_ID_DISP1, 0);
reset_set_enable(PERIPH_ID_PWM, 0);
reset_set_enable(PERIPH_ID_DPAUX, 0);
reset_set_enable(PERIPH_ID_SOR0, 0);
ret = display_init(dev, lcdbase, 1 << l2bpp, &timing);
if (ret)
return ret;
uc_priv->xsize = roundup(timing.hactive.typ, 16);
uc_priv->ysize = timing.vactive.typ;
uc_priv->bpix = l2bpp;
video_set_flush_dcache(dev, 1);
debug("%s: done\n", __func__);
return 0;
}
void nvhost_module_busy(struct nvhost_module *mod)
{
mutex_lock(&mod->lock);
cancel_delayed_work(&mod->powerdown);
if (mod->desc->busy)
mod->desc->busy(mod);
if ((atomic_inc_return(&mod->refcount) == 1) && !mod->powered) {
if (mod->parent)
nvhost_module_busy(mod->parent);
unpowergate(mod);
clock_enable(mod);
if (mod->desc->finalize_poweron)
mod->desc->finalize_poweron(mod);
mod->powered = true;
}
mutex_unlock(&mod->lock);
}
void uart1_clock_init(void)
{
clock_enable(UART1_CLK);
clock_set_rate(UART1_CLK, 19200000 / 4);
}
void uart2_clock_init(void)
{
clock_enable(UART2_CLK);
clock_set_rate(UART2_CLK, 19200000);
}
void mdp_clock_init(unsigned rate)
{
clock_set_rate(MDP_CLK, rate);
clock_enable(MDP_CLK);
clock_enable(MDP_P_CLK);
}
void lcdc_clock_init(unsigned rate)
{
clock_set_rate(MDP_LCDC_PCLK_CLK, rate);
clock_enable(MDP_LCDC_PCLK_CLK);
clock_enable(MDP_LCDC_PAD_PCLK_CLK);
}
void usb_clock_init()
{
clock_enable(USB_HS_PCLK);
clock_enable(USB_HS_CLK);
clock_enable(P_USB_HS_CORE_CLK);
}
/* set up the UTMI USB controller with the parameters provided */
static int init_utmi_usb_controller(struct fdt_usb *config)
{
u32 val;
int loop_count;
const unsigned *timing;
struct usb_ctlr *usbctlr = config->reg;
struct clk_rst_ctlr *clkrst;
struct usb_ctlr *usb1ctlr;
clock_enable(config->periph_id);
/* Reset the usb controller */
usbf_reset_controller(config, usbctlr);
/* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
/* Follow the crystal clock disable by >100ns delay */
udelay(1);
/*
* To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
* mux must be switched to actually use a_sess_vld threshold.
*/
if (config->dr_mode == DR_MODE_OTG &&
fdt_gpio_isvalid(&config->vbus_gpio))
clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
VBUS_SENSE_CTL_MASK,
VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
/*
* PLL Delay CONFIGURATION settings. The following parameters control
* the bring up of the plls.
*/
timing = get_pll_timing();
if (!controller->has_hostpc) {
val = readl(&usbctlr->utmip_misc_cfg1);
clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
timing[PARAM_STABLE_COUNT] <<
UTMIP_PLLU_STABLE_COUNT_SHIFT);
clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
timing[PARAM_ACTIVE_DELAY_COUNT] <<
UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
writel(val, &usbctlr->utmip_misc_cfg1);
/* Set PLL enable delay count and crystal frequency count */
val = readl(&usbctlr->utmip_pll_cfg1);
clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
timing[PARAM_ENABLE_DELAY_COUNT] <<
UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
timing[PARAM_XTAL_FREQ_COUNT] <<
UTMIP_XTAL_FREQ_COUNT_SHIFT);
writel(val, &usbctlr->utmip_pll_cfg1);
} else {
clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
val = readl(&clkrst->crc_utmip_pll_cfg2);
clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
timing[PARAM_STABLE_COUNT] <<
UTMIP_PLLU_STABLE_COUNT_SHIFT);
clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
timing[PARAM_ACTIVE_DELAY_COUNT] <<
UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
writel(val, &clkrst->crc_utmip_pll_cfg2);
/* Set PLL enable delay count and crystal frequency count */
val = readl(&clkrst->crc_utmip_pll_cfg1);
clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
timing[PARAM_ENABLE_DELAY_COUNT] <<
UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
timing[PARAM_XTAL_FREQ_COUNT] <<
UTMIP_XTAL_FREQ_COUNT_SHIFT);
writel(val, &clkrst->crc_utmip_pll_cfg1);
/* Disable Power Down state for PLL */
clrbits_le32(&clkrst->crc_utmip_pll_cfg1,
PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN |
PLL_ACTIVE_POWERDOWN);
/* Recommended PHY settings for EYE diagram */
val = readl(&usbctlr->utmip_xcvr_cfg0);
clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK,
0x4 << UTMIP_XCVR_SETUP_SHIFT);
clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK,
0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT);
clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK,
0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT);
writel(val, &usbctlr->utmip_xcvr_cfg0);
clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1,
UTMIP_XCVR_TERM_RANGE_ADJ_MASK,
0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT);
/* Some registers can be controlled from USB1 only. */
if (config->periph_id != PERIPH_ID_USBD) {
clock_enable(PERIPH_ID_USBD);
/* Disable Reset if in Reset state */
reset_set_enable(PERIPH_ID_USBD, 0);
}
usb1ctlr = (struct usb_ctlr *)
((u32)config->reg & USB1_ADDR_MASK);
val = readl(&usb1ctlr->utmip_bias_cfg0);
setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB);
clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK,
0x1 << UTMIP_HSDISCON_LEVEL_SHIFT);
clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK,
0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT);
writel(val, &usb1ctlr->utmip_bias_cfg0);
/* Miscellaneous setting mentioned in Programming Guide */
clrbits_le32(&usbctlr->utmip_misc_cfg0,
UTMIP_SUSPEND_EXIT_ON_EDGE);
}
/* Setting the tracking length time */
clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
UTMIP_BIAS_PDTRK_COUNT_MASK,
timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
/* Program debounce time for VBUS to become valid */
clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
UTMIP_DEBOUNCE_CFG0_MASK,
timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
/* Disable battery charge enabling bit */
setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
/*
* Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
* Setting these fields, together with default values of the
* other fields, results in programming the registers below as
* follows:
* UTMIP_HSRX_CFG0 = 0x9168c000
* UTMIP_HSRX_CFG1 = 0x13
*/
/* Set PLL enable delay count and Crystal frequency count */
val = readl(&usbctlr->utmip_hsrx_cfg0);
clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
writel(val, &usbctlr->utmip_hsrx_cfg0);
/* Configure the UTMIP_HS_SYNC_START_DLY */
clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
UTMIP_HS_SYNC_START_DLY_MASK,
utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
/* Preceed the crystal clock disable by >100ns delay. */
udelay(1);
/* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
if (controller->has_hostpc) {
if (config->periph_id == PERIPH_ID_USBD)
clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
UTMIP_FORCE_PD_SAMP_A_POWERDOWN);
if (config->periph_id == PERIPH_ID_USB3)
clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
UTMIP_FORCE_PD_SAMP_C_POWERDOWN);
}
/* Finished the per-controller init. */
/* De-assert UTMIP_RESET to bring out of reset. */
clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
/* Wait for the phy clock to become valid in 100 ms */
for (loop_count = 100000; loop_count != 0; loop_count--) {
if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
break;
udelay(1);
}
if (!loop_count)
return -1;
/* Disable ICUSB FS/LS transceiver */
clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
/* Select UTMI parallel interface */
clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
PTS_UTMI << PTS_SHIFT);
clrbits_le32(&usbctlr->port_sc1, STS);
/* Deassert power down state */
clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
if (controller->has_hostpc) {
/*
* BIAS Pad Power Down is common among all 3 USB
* controllers and can be controlled from USB1 only.
*/
usb1ctlr = (struct usb_ctlr *)
((u32)config->reg & USB1_ADDR_MASK);
clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD);
udelay(25);
clrbits_le32(&usb1ctlr->utmip_bias_cfg1,
UTMIP_FORCE_PDTRK_POWERDOWN);
}
return 0;
}
/* set up the UTMI USB controller with the parameters provided */
static int init_utmi_usb_controller(struct fdt_usb *config,
struct usb_ctlr *usbctlr, const u32 timing[])
{
u32 val;
int loop_count;
clock_enable(config->periph_id);
/* Reset the usb controller */
usbf_reset_controller(config, usbctlr);
/* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
/* Follow the crystal clock disable by >100ns delay */
udelay(1);
/*
* To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
* mux must be switched to actually use a_sess_vld threshold.
*/
if (fdt_gpio_isvalid(&config->vbus_gpio)) {
clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
VBUS_SENSE_CTL_MASK,
VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
}
/*
* PLL Delay CONFIGURATION settings. The following parameters control
* the bring up of the plls.
*/
val = readl(&usbctlr->utmip_misc_cfg1);
clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT);
clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
timing[PARAM_ACTIVE_DELAY_COUNT] <<
UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
writel(val, &usbctlr->utmip_misc_cfg1);
/* Set PLL enable delay count and crystal frequency count */
val = readl(&usbctlr->utmip_pll_cfg1);
clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
timing[PARAM_ENABLE_DELAY_COUNT] <<
UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
timing[PARAM_XTAL_FREQ_COUNT] <<
UTMIP_XTAL_FREQ_COUNT_SHIFT);
writel(val, &usbctlr->utmip_pll_cfg1);
/* Setting the tracking length time */
clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
UTMIP_BIAS_PDTRK_COUNT_MASK,
timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
/* Program debounce time for VBUS to become valid */
clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
UTMIP_DEBOUNCE_CFG0_MASK,
timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
/* Disable battery charge enabling bit */
setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
/*
* Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
* Setting these fields, together with default values of the
* other fields, results in programming the registers below as
* follows:
* UTMIP_HSRX_CFG0 = 0x9168c000
* UTMIP_HSRX_CFG1 = 0x13
*/
/* Set PLL enable delay count and Crystal frequency count */
val = readl(&usbctlr->utmip_hsrx_cfg0);
clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
writel(val, &usbctlr->utmip_hsrx_cfg0);
/* Configure the UTMIP_HS_SYNC_START_DLY */
clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
UTMIP_HS_SYNC_START_DLY_MASK,
utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
/* Preceed the crystal clock disable by >100ns delay. */
udelay(1);
/* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
/* Finished the per-controller init. */
/* De-assert UTMIP_RESET to bring out of reset. */
clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
/* Wait for the phy clock to become valid in 100 ms */
for (loop_count = 100000; loop_count != 0; loop_count--) {
if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
break;
udelay(1);
}
if (!loop_count)
return -1;
/* Disable ICUSB FS/LS transceiver */
clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
/* Select UTMI parallel interface */
clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
PTS_UTMI << PTS_SHIFT);
clrbits_le32(&usbctlr->port_sc1, STS);
/* Deassert power down state */
clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
return 0;
}
/* Legacy function to allow drivers to enable their clock */
void u8500_clock_enable(int periph, int cluster, int kern)
{
clock_enable(periph, cluster, kern);
}
void mddi_init(void)
{
unsigned n;
dprintf("mddi_init() configuring for LCDC\n");
/* MDP init */
/* seems like not needed */
/* LCDC init */
#if 0
clock_enable(MDP_LCDC_PCLK_CLK);
clock_enable(MDP_LCDC_PAD_PCLK_CLK);
clock_set_rate(MDP_LCDC_PCLK_CLK, 74250000);
clock_set_rate(MDP_LCDC_PAD_PCLK_CLK, 74250000);
#endif
lcdc_clock_init();
writel(LCDC_FB_PHYS, MSM_MDP_BASE1 + 0x90008);
writel((LCDC_FB_HEIGHT << 16) | LCDC_FB_WIDTH, MSM_MDP_BASE1 + 0x90004);
writel(LCDC_FB_WIDTH * LCDC_FB_BPP / 8, MSM_MDP_BASE1 + 0x9000c);
writel(0, MSM_MDP_BASE1 + 0x90010);
writel(DMA_PACK_ALIGN_LSB|DMA_PACK_PATTERN_RGB|DMA_DITHER_EN|
DMA_OUT_SEL_LCDC|DMA_IBUF_FORMAT_RGB565|
DMA_DSTC0G_8BITS|DMA_DSTC1B_8BITS|DMA_DSTC2R_8BITS,
MSM_MDP_BASE1 + 0x90000);
int hsync_period = LCDC_HSYNC_PULSE_WIDTH_DCLK + LCDC_HSYNC_BACK_PORCH_DCLK + LCDC_FB_WIDTH + LCDC_HSYNC_FRONT_PORCH_DCLK;
int vsync_period = (LCDC_VSYNC_PULSE_WIDTH_LINES + LCDC_VSYNC_BACK_PORCH_LINES + LCDC_FB_HEIGHT + LCDC_VSYNC_FRONT_PORCH_LINES) * hsync_period;
int hsync_ctrl = (hsync_period << 16) | LCDC_HSYNC_PULSE_WIDTH_DCLK;
int hsync_start_x = LCDC_HSYNC_PULSE_WIDTH_DCLK + LCDC_HSYNC_BACK_PORCH_DCLK;
int hsync_end_x = hsync_period - LCDC_HSYNC_FRONT_PORCH_DCLK - 1;
int display_hctl = (hsync_end_x << 16) | hsync_start_x;
int display_vstart= (LCDC_VSYNC_PULSE_WIDTH_LINES + LCDC_VSYNC_BACK_PORCH_LINES) * hsync_period + LCDC_HSYNC_SKEW_DCLK;
int display_vend = vsync_period - (LCDC_VSYNC_FRONT_PORCH_LINES * hsync_period) + LCDC_HSYNC_SKEW_DCLK - 1;
writel((hsync_period << 16) | LCDC_HSYNC_PULSE_WIDTH_DCLK, MSM_MDP_BASE1 + 0xe0004);
writel(vsync_period, MSM_MDP_BASE1 + 0xe0008);
writel(LCDC_VSYNC_PULSE_WIDTH_LINES * hsync_period, MSM_MDP_BASE1 + 0xe000c);
writel(display_hctl, MSM_MDP_BASE1 + 0xe0010);
writel(display_vstart, MSM_MDP_BASE1 + 0xe0014);
writel(display_vend, MSM_MDP_BASE1 + 0xe0018);
writel(0, MSM_MDP_BASE1 + 0xe0028);
writel(0xff, MSM_MDP_BASE1 + 0xe002c);
writel(LCDC_HSYNC_SKEW_DCLK, MSM_MDP_BASE1 + 0xe0030);
writel(0, MSM_MDP_BASE1 + 0xe0038);
writel(0, MSM_MDP_BASE1 + 0xe001c);
writel(0, MSM_MDP_BASE1 + 0xe0020);
writel(0, MSM_MDP_BASE1 + 0xe0024);
writel(1, MSM_MDP_BASE1 + 0xe0000);
//clock_enable(MDP_CLK);
mdp_clock_init();
//panel_backlight(0);
//panel_poweron();
fb_width = LCDC_FB_WIDTH;
fb_height = LCDC_FB_HEIGHT;
dprintf("panel is %d x %d\n", fb_width, fb_height);
FB = LCDC_FB_PHYS; //alloc(2 * fb_width * fb_height);
for(n = 0; n < (fb_width * fb_height); n++) FB[n] = 0;
gpio_set(32, 1);
gpio_dir(32, 1);
mdelay(100);
gpio_set(20, 1);
gpio_dir(20, 1);
mdelay(100);
gpio_set(155, 1);
gpio_dir(155, 1);
//gpio_set(61, 1);
}
/* Main clock init function. Called from arch_cpu_init() */
void db8500_clocks_init(void)
{
/*
* Enable all clocks. This is u-boot, we can enable it all. There is no
* powersave in u-boot.
*/
clock_enable(1, 9, -1); /* GPIO0 */
if (u8500_is_earlydrop())
clock_enable(2, 12, -1); /* GPIO1 */
else
clock_enable(2, 11, -1); /* GPIO1 */
clock_enable(3, 8, -1); /* GPIO2 */
clock_enable(5, 1, -1); /* GPIO3 */
clock_enable(3, 6, 6); /* UART2 */
clock_enable(3, 3, 3); /* I2C0 */
clock_enable(1, 5, 5); /* SDI0 */
clock_enable(2, 4, 2); /* SDI4 */
if (u8500_is_earlydrop())
clock_enable(7, 2, -1); /* MTU0 */
else if (cpu_is_u8500v1())
clock_enable(6, 7, -1); /* MTU0 */
else if (cpu_is_u8500v2() || cpu_is_u9540v10())
clock_enable(6, 6, -1); /* MTU0 */
if (!u8500_is_earlydrop())
clock_enable(3, 4, 4); /* SDI2 */
/*
* Enabling clocks for all devices which are AMBA devices in the
* kernel. Otherwise they will not get probe()'d because the
* peripheral ID register will not be powered.
*/
/* XXX: some of these differ between ED/V1 */
clock_enable(1, 1, 1); /* UART1 */
clock_enable(1, 0, 0); /* UART0 */
clock_enable(3, 2, 2); /* SSP1 */
clock_enable(3, 1, 1); /* SSP0 */
clock_enable(2, 8, -1); /* SPI0 */
clock_enable(2, 5, 3); /* MSP2 */
}
static void enable_cpu_clocks(void)
{
clock_enable(CLK_ENB_CPU, 0, 0, SET_CLK_ENB_CPUG_ENABLE |
SET_CLK_ENB_CPULP_ENABLE, 0, 0, 0);
}
/* set up the ULPI USB controller with the parameters provided */
static int init_ulpi_usb_controller(struct fdt_usb *config,
struct usb_ctlr *usbctlr)
{
u32 val;
int loop_count;
struct ulpi_viewport ulpi_vp;
/* set up ULPI reference clock on pllp_out4 */
clock_enable(PERIPH_ID_DEV2_OUT);
clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK);
/* reset ULPI phy */
if (fdt_gpio_isvalid(&config->phy_reset_gpio)) {
fdtdec_setup_gpio(&config->phy_reset_gpio);
gpio_direction_output(config->phy_reset_gpio.gpio, 0);
mdelay(5);
gpio_set_value(config->phy_reset_gpio.gpio, 1);
}
/* Reset the usb controller */
clock_enable(config->periph_id);
usbf_reset_controller(config, usbctlr);
/* enable pinmux bypass */
setbits_le32(&usbctlr->ulpi_timing_ctrl_0,
ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
/* Select ULPI parallel interface */
clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
/* enable ULPI transceiver */
setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
/* configure ULPI transceiver timings */
val = 0;
writel(val, &usbctlr->ulpi_timing_ctrl_1);
val |= ULPI_DATA_TRIMMER_SEL(4);
val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
val |= ULPI_DIR_TRIMMER_SEL(4);
writel(val, &usbctlr->ulpi_timing_ctrl_1);
udelay(10);
val |= ULPI_DATA_TRIMMER_LOAD;
val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
val |= ULPI_DIR_TRIMMER_LOAD;
writel(val, &usbctlr->ulpi_timing_ctrl_1);
/* set up phy for host operation with external vbus supply */
ulpi_vp.port_num = 0;
ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport;
if (ulpi_init(&ulpi_vp)) {
printf("Tegra ULPI viewport init failed\n");
return -1;
}
ulpi_set_vbus(&ulpi_vp, 1, 1);
ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0);
/* enable wakeup events */
setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC);
/* Enable and wait for the phy clock to become valid in 100 ms */
setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
for (loop_count = 100000; loop_count != 0; loop_count--) {
if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
break;
udelay(1);
}
if (!loop_count)
return -1;
clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
return 0;
}
/* set up the UTMI USB controller with the parameters provided */
static int init_utmi_usb_controller(struct fdt_usb *config,
enum usb_init_type init)
{
struct fdt_usb_controller *controller;
u32 b_sess_valid_mask, val;
int loop_count;
const unsigned *timing;
struct usb_ctlr *usbctlr = config->reg;
struct clk_rst_ctlr *clkrst;
struct usb_ctlr *usb1ctlr;
clock_enable(config->periph_id);
/* Reset the usb controller */
usbf_reset_controller(config, usbctlr);
/* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
/* Follow the crystal clock disable by >100ns delay */
udelay(1);
b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN);
clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask,
(init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0);
/*
* To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
* mux must be switched to actually use a_sess_vld threshold.
*/
if (config->dr_mode == DR_MODE_OTG &&
dm_gpio_is_valid(&config->vbus_gpio))
clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
VBUS_SENSE_CTL_MASK,
VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
controller = &fdt_usb_controllers[config->type];
debug("controller=%p, type=%d\n", controller, config->type);
/*
* PLL Delay CONFIGURATION settings. The following parameters control
* the bring up of the plls.
*/
timing = get_pll_timing(controller);
if (!controller->has_hostpc) {
val = readl(&usbctlr->utmip_misc_cfg1);
clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
timing[PARAM_STABLE_COUNT] <<
UTMIP_PLLU_STABLE_COUNT_SHIFT);
clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
timing[PARAM_ACTIVE_DELAY_COUNT] <<
UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
writel(val, &usbctlr->utmip_misc_cfg1);
/* Set PLL enable delay count and crystal frequency count */
val = readl(&usbctlr->utmip_pll_cfg1);
clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
timing[PARAM_ENABLE_DELAY_COUNT] <<
UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
timing[PARAM_XTAL_FREQ_COUNT] <<
UTMIP_XTAL_FREQ_COUNT_SHIFT);
writel(val, &usbctlr->utmip_pll_cfg1);
} else {
clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
val = readl(&clkrst->crc_utmip_pll_cfg2);
clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
timing[PARAM_STABLE_COUNT] <<
UTMIP_PLLU_STABLE_COUNT_SHIFT);
clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
timing[PARAM_ACTIVE_DELAY_COUNT] <<
UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
writel(val, &clkrst->crc_utmip_pll_cfg2);
/* Set PLL enable delay count and crystal frequency count */
val = readl(&clkrst->crc_utmip_pll_cfg1);
clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
timing[PARAM_ENABLE_DELAY_COUNT] <<
UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
timing[PARAM_XTAL_FREQ_COUNT] <<
UTMIP_XTAL_FREQ_COUNT_SHIFT);
writel(val, &clkrst->crc_utmip_pll_cfg1);
/* Disable Power Down state for PLL */
clrbits_le32(&clkrst->crc_utmip_pll_cfg1,
PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN |
PLL_ACTIVE_POWERDOWN);
/* Recommended PHY settings for EYE diagram */
val = readl(&usbctlr->utmip_xcvr_cfg0);
clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK,
0x4 << UTMIP_XCVR_SETUP_SHIFT);
clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK,
0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT);
clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK,
0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT);
writel(val, &usbctlr->utmip_xcvr_cfg0);
clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1,
UTMIP_XCVR_TERM_RANGE_ADJ_MASK,
0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT);
/* Some registers can be controlled from USB1 only. */
if (config->periph_id != PERIPH_ID_USBD) {
clock_enable(PERIPH_ID_USBD);
/* Disable Reset if in Reset state */
reset_set_enable(PERIPH_ID_USBD, 0);
}
usb1ctlr = (struct usb_ctlr *)
((unsigned long)config->reg & USB1_ADDR_MASK);
val = readl(&usb1ctlr->utmip_bias_cfg0);
setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB);
clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK,
0x1 << UTMIP_HSDISCON_LEVEL_SHIFT);
clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK,
0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT);
writel(val, &usb1ctlr->utmip_bias_cfg0);
/* Miscellaneous setting mentioned in Programming Guide */
clrbits_le32(&usbctlr->utmip_misc_cfg0,
UTMIP_SUSPEND_EXIT_ON_EDGE);
}
/* Setting the tracking length time */
clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
UTMIP_BIAS_PDTRK_COUNT_MASK,
timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
/* Program debounce time for VBUS to become valid */
clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
UTMIP_DEBOUNCE_CFG0_MASK,
timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
if (timing[PARAM_DEBOUNCE_A_TIME] > 0xFFFF) {
clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
UTMIP_DEBOUNCE_CFG0_MASK,
(timing[PARAM_DEBOUNCE_A_TIME] >> 1)
<< UTMIP_DEBOUNCE_CFG0_SHIFT);
clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK,
1 << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT);
}