static void setup_usb(void)
{
clock_enable_clear_reset(CLK_L_USBD, CLK_H_USB3, 0, 0, 0, 0);
usb_setup_utmip((void *)TEGRA_USBD_BASE);
usb_setup_utmip((void *)TEGRA_USB3_BASE);
}
void early_mainboard_init(void)
{
clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0);
setup_pinmux();
configure_ec_spi_bus();
configure_tpm_i2c_bus();
}
/* Start PLLM for SDRAM. */
void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,
u32 ph135, u32 kvco, u32 kcp, u32 stable_time, u32 emc_source,
u32 same_freq)
{
u32 misc1 = ((setup << PLLM_MISC1_SETUP_SHIFT) |
(ph45 << PLLM_MISC1_PD_LSHIFT_PH45_SHIFT) |
(ph90 << PLLM_MISC1_PD_LSHIFT_PH90_SHIFT) |
(ph135 << PLLM_MISC1_PD_LSHIFT_PH135_SHIFT)),
misc2 = ((kvco << PLLM_MISC2_KVCO_SHIFT) |
(kcp << PLLM_MISC2_KCP_SHIFT)),
base;
if (same_freq)
emc_source |= CLK_SOURCE_EMC_MC_EMC_SAME_FREQ;
else
emc_source &= ~CLK_SOURCE_EMC_MC_EMC_SAME_FREQ;
/*
* Note PLLM_BASE.PLLM_OUT1_RSTN must be in RESET_ENABLE mode, and
* PLLM_BASE.ENABLE must be in DISABLE state (both are the default
* values after coldboot reset).
*/
write32(&clk_rst->pllm_misc1, misc1);
write32(&clk_rst->pllm_misc2, misc2);
/* PLLM.BASE needs BYPASS=0, different from general init_pll */
base = read32(&clk_rst->pllm_base);
base &= ~(PLLCMX_BASE_DIVN_MASK | PLLCMX_BASE_DIVM_MASK |
PLLM_BASE_DIVP_MASK | PLL_BASE_BYPASS);
base |= ((m << PLL_BASE_DIVM_SHIFT) | (n << PLL_BASE_DIVN_SHIFT) |
(p << PLL_BASE_DIVP_SHIFT));
write32(&clk_rst->pllm_base, base);
setbits_le32(&clk_rst->pllm_base, PLL_BASE_ENABLE);
/* stable_time is required, before we can start to check lock. */
udelay(stable_time);
while (!(read32(&clk_rst->pllm_base) & PLL_BASE_LOCK)) {
udelay(1);
}
/*
* After PLLM reports being locked, we have to delay 10us before
* enabling PLLM_OUT.
*/
udelay(10);
/* Put OUT1 out of reset state (start to output). */
setbits_le32(&clk_rst->pllm_out, PLLM_OUT1_RSTN_RESET_DISABLE);
/* Enable and start MEM(MC) and EMC. */
clock_enable_clear_reset(0, CLK_H_MEM | CLK_H_EMC, 0, 0, 0, 0);
write32(&clk_rst->clk_src_emc, emc_source);
udelay(IO_STABILIZATION_DELAY);
}
static void mainboard_init(device_t dev)
{
set_clock_sources();
clock_external_output(1); /* For external MAX98090 audio codec. */
/*
* Confirmed by NVIDIA hardware team, we need to take ALL audio devices
* conntected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out
* of reset and clock-enabled, otherwise reading AHUB devices (In our
* case, I2S/APBIF/AUDIO<XBAR>) will hang.
*
* Note that CLK_H_MEM (MC) and CLK_H_EMC should be already either
* initialized by BootROM, or in romstage SDRAM initialization.
*/
clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | CLK_L_SDMMC4 |
CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 |
CLK_L_SPDIF | CLK_L_USBD | CLK_L_DISP1 |
CLK_L_HOST1X | CLK_L_PWM,
CLK_H_I2C2 | CLK_H_PMC | CLK_H_USB3,
CLK_U_CSITE | CLK_U_SDMMC3,
CLK_V_I2C4 | CLK_V_EXTPERIPH1 | CLK_V_APBIF |
CLK_V_AUDIO | CLK_V_I2S3 | CLK_V_I2S4 |
CLK_V_DAM0 | CLK_V_DAM1 | CLK_V_DAM2,
CLK_W_DVFS | CLK_W_AMX0 | CLK_W_ADX0,
CLK_X_DPAUX | CLK_X_SOR0 | CLK_X_AMX1 |
CLK_X_ADX1 | CLK_X_AFC0 | CLK_X_AFC1 |
CLK_X_AFC2 | CLK_X_AFC3 | CLK_X_AFC4 |
CLK_X_AFC5);
usb_setup_utmip((void*)TEGRA_USBD_BASE);
/* USB2 is the camera, we don't need it in firmware */
usb_setup_utmip((void*)TEGRA_USB3_BASE);
setup_pinmux();
i2c_init(0);
i2c_init(1);
i2c_init(3);
setup_kernel_info();
clock_init_arm_generic_timer();
setup_ec_spi();
#if CONFIG_ELOG
elog_init();
elog_add_boot_reason();
#endif
}
static void configure_display_clocks(void)
{
u32 lclks = CLK_L_HOST1X | CLK_L_DISP1; /* dc */
u32 hclks = CLK_H_MIPI_CAL | CLK_H_DSI; /* mipi phy, mipi-dsi a */
u32 uclks = CLK_U_DSIB; /* mipi-dsi b */
u32 xclks = CLK_X_CLK72MHZ; /* clk src of mipi_cal */
clock_enable_clear_reset(lclks, hclks, uclks, 0, 0, xclks);
/* Give clocks time to stabilize. */
udelay(IO_STABILIZATION_DELAY);
}
static void configure_display_clocks(void)
{
u32 lclks = CLK_L_HOST1X | CLK_L_DISP1; /* dc */
u32 hclks = CLK_H_MIPI_CAL | CLK_H_DSI; /* mipi phy, mipi-dsi a */
u32 uclks = CLK_U_DSIB; /* mipi-dsi b */
u32 xclks = CLK_X_UART_FST_MIPI_CAL; /* uart_fst_mipi_cal */
clock_enable_clear_reset(lclks, hclks, uclks, 0, 0, xclks, 0);
/* Give clocks time to stabilize. */
udelay(IO_STABILIZATION_DELAY);
/* CLK72MHZ_CLK_SRC */
clock_configure_source(uart_fst_mipi_cal, PLLP_OUT3, 68000);
}
/* Enable/unreset all audio toys under AHUB */
void clock_enable_audio(void)
{
/*
* Confirmed by NVIDIA hardware team, we need to take ALL audio devices
* connected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out
* of reset and clock-enabled, otherwise reading AHUB devices (in our
* case, I2S/APBIF/AUDIO<XBAR>) will hang.
*/
clock_enable_clear_reset(CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 | CLK_L_SPDIF,
0, 0,
CLK_V_I2S3 | CLK_V_I2S4 | CLK_V_AUDIO | CLK_V_APBIF |
CLK_V_DAM0 | CLK_V_DAM1 | CLK_V_DAM2 | CLK_V_EXTPERIPH1,
CLK_W_AMX0 | CLK_W_ADX0,
CLK_X_ADX1 | CLK_X_AFC0 | CLK_X_AFC1 | CLK_X_AFC2 |
CLK_X_AFC3 | CLK_X_AFC4 | CLK_X_AFC5 | CLK_X_AMX1);
}
static void mainboard_init(device_t dev)
{
set_clock_sources();
clock_external_output(1); /* For external MAX98090 audio codec. */
/*
* Confirmed by NVIDIA hardware team, we need to take ALL audio devices
* conntected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out
* of reset and clock-enabled, otherwise reading AHUB devices (In our
* case, I2S/APBIF/AUDIO<XBAR>) will hang.
*/
clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | CLK_L_SDMMC4 |
CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 |
CLK_L_SPDIF | CLK_L_USBD | CLK_L_DISP1 |
CLK_L_HOST1X | CLK_L_PWM,
CLK_H_EMC | CLK_H_I2C2 | CLK_H_PMC |
CLK_H_MEM | CLK_H_USB2 | CLK_H_USB3,
CLK_U_CSITE | CLK_U_SDMMC3,
CLK_V_I2C4 | CLK_V_EXTPERIPH1 | CLK_V_APBIF |
CLK_V_AUDIO | CLK_V_I2S3 | CLK_V_I2S4 |
CLK_V_DAM0 | CLK_V_DAM1 | CLK_V_DAM2,
CLK_W_DVFS | CLK_W_AMX0 | CLK_W_ADX0,
CLK_X_DPAUX | CLK_X_SOR0 | CLK_X_AMX1 |
CLK_X_ADX1 | CLK_X_AFC0 | CLK_X_AFC1 |
CLK_X_AFC2 | CLK_X_AFC3 | CLK_X_AFC4 |
CLK_X_AFC5);
usb_setup_utmip((void*)TEGRA_USBD_BASE);
usb_setup_utmip((void*)TEGRA_USB2_BASE);
usb_setup_utmip((void*)TEGRA_USB3_BASE);
setup_pinmux();
i2c_init(0);
i2c_init(1);
i2c_init(3);
setup_kernel_info();
clock_init_arm_generic_timer();
setup_ec_spi();
}
void bootblock_mainboard_init(void)
{
set_clock_sources();
clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR,
CLK_H_I2C5 | CLK_H_APBDMA,
0, CLK_V_MSELECT, 0, 0);
// Board ID GPIOs, bits 0-3.
gpio_input(GPIO(Q3));
gpio_input(GPIO(T1));
gpio_input(GPIO(X1));
gpio_input(GPIO(X4));
// I2C5 (PMU) clock.
pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX,
PINMUX_PWR_I2C_SCL_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
// I2C5 (PMU) data.
pinmux_set_config(PINMUX_PWR_I2C_SDA_INDEX,
PINMUX_PWR_I2C_SDA_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
i2c_init(4);
pmic_init(4);
/* SPI4 data out (MOSI) */
pinmux_set_config(PINMUX_GPIO_PG6_INDEX,
PINMUX_GPIO_PG6_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
PINMUX_PULL_UP);
/* SPI4 data in (MISO) */
pinmux_set_config(PINMUX_GPIO_PG7_INDEX,
PINMUX_GPIO_PG7_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
PINMUX_PULL_UP);
/* SPI4 clock */
pinmux_set_config(PINMUX_GPIO_PG5_INDEX,
PINMUX_GPIO_PG5_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
/* SPI4 chip select 0 */
pinmux_set_config(PINMUX_GPIO_PI3_INDEX,
PINMUX_GPIO_PI3_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
tegra_spi_init(4);
}
void main(void)
{
// enable JTAG at the earliest stage
enable_jtag();
clock_early_uart();
/* Configure mselect clock. */
clock_configure_source(mselect, PLLP, 102000);
/* Enable AVP cache, timer, APB dma, and mselect blocks. */
clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR,
CLK_H_APBDMA,
0, CLK_V_MSELECT, 0, 0);
/* Find ODMDATA in IRAM and save it to scratch reg */
save_odmdata();
bootblock_mainboard_early_init();
if (CONFIG_BOOTBLOCK_CONSOLE) {
console_init();
exception_init();
printk(BIOS_INFO, "T132: Bootblock here\n");
}
clock_init();
printk(BIOS_INFO, "T132 bootblock: Clock init done\n");
pmc_print_rst_status();
bootblock_mainboard_init();
printk(BIOS_INFO, "T132 bootblock: Mainboard bootblock init done\n");
run_romstage();
}
