void main(void)
{
struct mem_timings *mem;
void *entry;
int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP);
/* Clock must be initialized before console_init, otherwise you may need
* to re-initialize serial console drivers again. */
mem = setup_clock();
console_init();
setup_power(is_resume);
setup_memory(mem, is_resume);
if (is_resume) {
wakeup();
}
setup_storage();
setup_gpio();
setup_graphics();
/* Set SPI (primary CBFS media) clock to 50MHz and configure pinmux. */
exynos_pinmux_spi1();
clock_set_rate(PERIPH_ID_SPI1, 50000000);
cbmem_initialize_empty();
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
stage_exit(entry);
}
void main(void)
{
extern struct mem_timings mem_timings;
void *entry;
int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP);
/* Clock must be initialized before console_init, otherwise you may need
* to re-initialize serial console drivers again. */
system_clock_init();
console_init();
setup_power(is_resume);
setup_memory(&mem_timings, is_resume);
primitive_mem_test();
if (is_resume) {
wakeup();
}
setup_storage();
setup_gpio();
setup_ec();
simple_spi_test();
/* Set SPI (primary CBFS media) clock to 50MHz. */
/* if this is uncommented SPI will not work correctly. */
clock_set_rate(PERIPH_ID_SPI1, 50000000);
simple_spi_test();
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
simple_spi_test();
stage_exit(entry);
}
static void setup_ec(void)
{
/* SPI2 (EC) is slower and needs to work in half-duplex mode with
* single byte bus width. */
clock_set_rate(PERIPH_ID_SPI2, 5000000);
exynos_pinmux_spi2();
}
void main(void)
{
extern struct mem_timings mem_timings;
int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP);
int power_init_failed;
exynos5420_config_smp();
power_init_failed = setup_power(is_resume);
timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
/* Clock must be initialized before console_init, otherwise you may need
* to re-initialize serial console drivers again. */
system_clock_init();
exynos_pinmux_uart3();
console_init();
exception_init();
if (power_init_failed)
die("Failed to intialize power.\n");
/* re-initialize PMIC I2C channel after (re-)setting system clocks */
i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */
timestamp_add_now(TS_BEFORE_INITRAM);
setup_memory(&mem_timings, is_resume);
timestamp_add_now(TS_AFTER_INITRAM);
primitive_mem_test();
trustzone_init();
if (is_resume) {
wakeup();
}
setup_gpio();
setup_ec();
simple_spi_test();
/* Set SPI (primary CBFS media) clock to 50MHz. */
/* if this is uncommented SPI will not work correctly. */
clock_set_rate(PERIPH_ID_SPI1, 50000000);
exynos_pinmux_spi1();
simple_spi_test();
cbmem_initialize_empty();
simple_spi_test();
timestamp_add_now(TS_END_ROMSTAGE);
run_ramstage();
}
void clock_early_init(void)
{
/*
* PLLP output frequency set to 216MHz
* PLLC output frequency set to 600Mhz
*
* TODO: Can we calculate these values instead of hard-coding?
*/
switch (clock_get_osc_freq()) {
case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
break;
case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
break;
case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
clock_set_rate(CLOCK_ID_PERIPH, 432, 13, 1, 8);
clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
break;
case CLOCK_OSC_FREQ_19_2:
default:
/*
* These are not supported. It is too early to print a
* message and the UART likely won't work anyway due to the
* oscillator being wrong.
*/
break;
}
}
void main(void)
{
struct mem_timings *mem;
struct arm_clk_ratios *arm_ratios;
int ret;
void *entry;
clock_set_rate(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
/* Clock must be initialized before console_init, otherwise you may need
* to re-initialize serial console drivers again. */
mem = get_mem_timings();
arm_ratios = get_arm_clk_ratios();
system_clock_init(mem, arm_ratios);
console_init();
/*
* FIXME: Do necessary I2C init so low-level PMIC code doesn't need to.
* Also, we should only call power_init() on cold boot.
*/
power_init();
if (!mem) {
printk(BIOS_CRIT, "Unable to auto-detect memory timings\n");
while(1);
}
printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n",
mem->mem_manuf,
mem->mem_type,
mem->mpll_mdiv,
mem->frequency_mhz);
ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE);
if (ret) {
printk(BIOS_ERR, "Memory controller init failed, err: %x\n",
ret);
while(1);
}
/* Set up MMU and caches */
mmu_setup_by_mva(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB);
initialize_s5p_mshc();
graphics();
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);
stage_exit(entry);
}
void mddi_clock_init(unsigned num, unsigned rate)
{
unsigned clock_id;
if (num == 0)
clock_id = PMDH_CLK;
else
clock_id = EMDH_CLK;
clock_enable(clock_id);
clock_set_rate(clock_id, rate);
#ifdef PLATFORM_MSM7X30
clock_enable(PMDH_P_CLK);
#endif
}
void main(void)
{
struct mem_timings *mem;
int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP);
timestamp_init(timestamp_get());
timestamp_add_now(TS_START_ROMSTAGE);
/* Clock must be initialized before console_init, otherwise you may need
* to re-initialize serial console drivers again. */
mem = setup_clock();
console_init();
exception_init();
setup_power(is_resume);
timestamp_add_now(TS_BEFORE_INITRAM);
setup_memory(mem, is_resume);
timestamp_add_now(TS_AFTER_INITRAM);
/* This needs to happen on normal boots and on resume. */
trustzone_init();
if (is_resume) {
wakeup();
}
setup_gpio();
setup_graphics();
/* Set SPI (primary CBFS media) clock to 50MHz and configure pinmux. */
exynos_pinmux_spi1();
clock_set_rate(PERIPH_ID_SPI1, 50000000);
cbmem_initialize_empty();
timestamp_add_now(TS_END_ROMSTAGE);
run_ramstage();
}
int mmc_clock_set_rate(unsigned id, unsigned rate)
{
return clock_set_rate(id, rate); //Set mmc clock rate
}
void uart1_clock_init(void)
{
clock_enable(UART1_CLK);
clock_set_rate(UART1_CLK, 19200000 / 4);
}
void uart2_clock_init(void)
{
clock_enable(UART2_CLK);
clock_set_rate(UART2_CLK, 19200000);
}
void mdp_clock_init(unsigned rate)
{
clock_set_rate(MDP_CLK, rate);
clock_enable(MDP_CLK);
clock_enable(MDP_P_CLK);
}
void lcdc_clock_init(unsigned rate)
{
clock_set_rate(MDP_LCDC_PCLK_CLK, rate);
clock_enable(MDP_LCDC_PCLK_CLK);
clock_enable(MDP_LCDC_PAD_PCLK_CLK);
}
void mddi_init(void)
{
unsigned n;
dprintf("mddi_init() configuring for LCDC\n");
/* MDP init */
/* seems like not needed */
/* LCDC init */
#if 0
clock_enable(MDP_LCDC_PCLK_CLK);
clock_enable(MDP_LCDC_PAD_PCLK_CLK);
clock_set_rate(MDP_LCDC_PCLK_CLK, 74250000);
clock_set_rate(MDP_LCDC_PAD_PCLK_CLK, 74250000);
#endif
lcdc_clock_init();
writel(LCDC_FB_PHYS, MSM_MDP_BASE1 + 0x90008);
writel((LCDC_FB_HEIGHT << 16) | LCDC_FB_WIDTH, MSM_MDP_BASE1 + 0x90004);
writel(LCDC_FB_WIDTH * LCDC_FB_BPP / 8, MSM_MDP_BASE1 + 0x9000c);
writel(0, MSM_MDP_BASE1 + 0x90010);
writel(DMA_PACK_ALIGN_LSB|DMA_PACK_PATTERN_RGB|DMA_DITHER_EN|
DMA_OUT_SEL_LCDC|DMA_IBUF_FORMAT_RGB565|
DMA_DSTC0G_8BITS|DMA_DSTC1B_8BITS|DMA_DSTC2R_8BITS,
MSM_MDP_BASE1 + 0x90000);
int hsync_period = LCDC_HSYNC_PULSE_WIDTH_DCLK + LCDC_HSYNC_BACK_PORCH_DCLK + LCDC_FB_WIDTH + LCDC_HSYNC_FRONT_PORCH_DCLK;
int vsync_period = (LCDC_VSYNC_PULSE_WIDTH_LINES + LCDC_VSYNC_BACK_PORCH_LINES + LCDC_FB_HEIGHT + LCDC_VSYNC_FRONT_PORCH_LINES) * hsync_period;
int hsync_ctrl = (hsync_period << 16) | LCDC_HSYNC_PULSE_WIDTH_DCLK;
int hsync_start_x = LCDC_HSYNC_PULSE_WIDTH_DCLK + LCDC_HSYNC_BACK_PORCH_DCLK;
int hsync_end_x = hsync_period - LCDC_HSYNC_FRONT_PORCH_DCLK - 1;
int display_hctl = (hsync_end_x << 16) | hsync_start_x;
int display_vstart= (LCDC_VSYNC_PULSE_WIDTH_LINES + LCDC_VSYNC_BACK_PORCH_LINES) * hsync_period + LCDC_HSYNC_SKEW_DCLK;
int display_vend = vsync_period - (LCDC_VSYNC_FRONT_PORCH_LINES * hsync_period) + LCDC_HSYNC_SKEW_DCLK - 1;
writel((hsync_period << 16) | LCDC_HSYNC_PULSE_WIDTH_DCLK, MSM_MDP_BASE1 + 0xe0004);
writel(vsync_period, MSM_MDP_BASE1 + 0xe0008);
writel(LCDC_VSYNC_PULSE_WIDTH_LINES * hsync_period, MSM_MDP_BASE1 + 0xe000c);
writel(display_hctl, MSM_MDP_BASE1 + 0xe0010);
writel(display_vstart, MSM_MDP_BASE1 + 0xe0014);
writel(display_vend, MSM_MDP_BASE1 + 0xe0018);
writel(0, MSM_MDP_BASE1 + 0xe0028);
writel(0xff, MSM_MDP_BASE1 + 0xe002c);
writel(LCDC_HSYNC_SKEW_DCLK, MSM_MDP_BASE1 + 0xe0030);
writel(0, MSM_MDP_BASE1 + 0xe0038);
writel(0, MSM_MDP_BASE1 + 0xe001c);
writel(0, MSM_MDP_BASE1 + 0xe0020);
writel(0, MSM_MDP_BASE1 + 0xe0024);
writel(1, MSM_MDP_BASE1 + 0xe0000);
//clock_enable(MDP_CLK);
mdp_clock_init();
//panel_backlight(0);
//panel_poweron();
fb_width = LCDC_FB_WIDTH;
fb_height = LCDC_FB_HEIGHT;
dprintf("panel is %d x %d\n", fb_width, fb_height);
FB = LCDC_FB_PHYS; //alloc(2 * fb_width * fb_height);
for(n = 0; n < (fb_width * fb_height); n++) FB[n] = 0;
gpio_set(32, 1);
gpio_dir(32, 1);
mdelay(100);
gpio_set(20, 1);
gpio_dir(20, 1);
mdelay(100);
gpio_set(155, 1);
gpio_dir(155, 1);
//gpio_set(61, 1);
}
