Exemple #1
0
static void all_exti_irqhandler( int line )
{
  u16 v, port, pin;
  
  v = exti_line_to_gpio( line );
  port = PLATFORM_IO_GET_PORT( v );
  pin = PLATFORM_IO_GET_PIN( v );

  if( EXTI->RTSR & (1 << line ) && platform_pio_op( port, 1 << pin, PLATFORM_IO_PIN_GET ) )
    cmn_int_handler( INT_GPIO_POSEDGE, v );
  if( EXTI->FTSR & (1 << line ) && ( platform_pio_op( port, 1 << pin, PLATFORM_IO_PIN_GET ) == 0 ) )
    cmn_int_handler( INT_GPIO_NEGEDGE, v );

  EXTI_ClearITPendingBit( exti_line[ line ] );
}
Exemple #2
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// EINT3 (INT_GPIO) interrupt handler
static void int_handler_eint3()
{
  elua_int_id id = ELUA_INT_INVALID_INTERRUPT;
  pio_code resnum = 0;
  int pidx, pin;
  
  EXTINT |= 1 << EINT3_BIT; // clear interrupt
  // Look for interrupt source
  // In can only be GPIO0/GPIO2, as the EXT interrupts are not (yet) used
  pidx = ( IO_INT_STAT & 1 ) ? 0 : 1;
  if( *posedge_status[ pidx ] )
  {
    id = INT_GPIO_POSEDGE;
    pin = intlog2( *posedge_status[ pidx ] );
  }
  else
  {
    id = INT_GPIO_NEGEDGE;
    pin = intlog2( *negedge_status[ pidx ] );
  }
  resnum = PLATFORM_IO_ENCODE( pidx * 2, pin, PLATFORM_IO_ENC_PIN );   
  *intclr_regs[ pidx ] = 1 << pin;
  
  // Run the interrupt through eLua
  cmn_int_handler( id, resnum );
  VICVectAddr = 0; // ACK interrupt    
}
static void gpio_common_handler( int port )
{
  u32 base = pio_base[ port ];
  u8 pin, pinmask;
  u32 ibe = HWREG( base + GPIO_O_IBE );
  u32 iev = HWREG( base + GPIO_O_IEV );

  // Check each pin in turn
  for( pin = 0, pinmask = 1; pin < 8; pin ++, pinmask <<= 1 )
    if( HWREG( base + GPIO_O_MIS ) & pinmask ) // interrupt on pin
    {
      if( MAP_GPIOPinRead( base, pinmask ) && ( ( ibe & pinmask ) || ( iev & pinmask ) ) ) // high level and posedge interrupt enabled 
        cmn_int_handler( INT_GPIO_POSEDGE, PLATFORM_IO_ENCODE( port, pin, 0 ) );
      else if( ( ibe & pinmask ) || !( iev & pinmask ) ) // low level and negedge interrupt enabled
        cmn_int_handler( INT_GPIO_NEGEDGE, PLATFORM_IO_ENCODE( port, pin, 0 ) );
      HWREG( base + GPIO_O_ICR ) = pinmask;
    }
}
Exemple #4
0
static void all_usart_irqhandler( int resnum )
{
  //int temp;

  //temp = USART_GetFlagStatus( stm32_usart[ resnum ], USART_FLAG_ORE );
  cmn_int_handler( INT_UART_RX, resnum );
  //if( temp == SET )
  //  for( temp = 0; temp < 10; temp ++ )
  //    platform_s_uart_send( resnum, '@' );
}
Exemple #5
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static void tmr_int_handler( unsigned id )
{
  TIM_TypeDef *base = ( TIM_TypeDef* )timer[ id ];

  if (TIM_GetITStatus( base, TIM_IT_CC1) != RESET)
  {
    TIM_ClearITPendingBit( base, TIM_IT_CC1 );

    if( id == VTMR_TIMER_ID )
      cmn_virtual_timer_cb();
    else
      cmn_int_handler( INT_TMR_MATCH, id );

    if( stm32_timer_int_periodic_flag[ id ] != PLATFORM_TIMER_INT_CYCLIC )
      TIM_ITConfig( base, TIM_IT_CC1, DISABLE );
  }
}
Exemple #6
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static void tmr_match_common_handler( int id )
{
  volatile avr32_tc_t *tc = &AVR32_TC;

  tc_read_sr( tc, id ); // clear interrupt
#if VTMR_NUM_TIMERS > 0
  if( id == VTMR_CH )
  {
    cmn_virtual_timer_cb();
    platform_eth_timer_handler();
    platform_cdc_timer_handler();
  }
  else
#endif
    cmn_int_handler( INT_TMR_MATCH, id );

  if( avr32_timer_int_periodic_flag[ id ] != PLATFORM_TIMER_INT_CYCLIC )
  {
    tc->channel[ id ].IDR.cpcs = 1;
    tc->channel[ id ].CMR.waveform.wavsel = TC_WAVEFORM_SEL_UP_MODE;
  }
}
static void uart_common_rx_handler( int resnum )
{
  MAP_UARTIntClear( uart_base[ resnum ], uart_int_mask );
  while( MAP_UARTCharsAvail( uart_base[ resnum ] ) )  
    cmn_int_handler( INT_UART_RX, resnum );  
}
Exemple #8
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static void uart_common_rx_handler( int resnum )
{
  cmn_int_handler( INT_UART_RX, resnum );
  AT91C_BASE_AIC->AIC_ICCR = 1 << usart_int_ids[ resnum ];
  AT91C_BASE_AIC->AIC_EOICR = 0;
}
Exemple #9
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// Common UART interrupt handler
static void uart_rx_common_handler( elua_int_resnum resnum )
{
  cmn_int_handler( INT_UART_RX, resnum );
  VICVectAddr = 0;
}
Exemple #10
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static void uart_common_rx_handler( int resnum )
{
  cmn_int_handler( INT_UART_RX, resnum );
}