/*
 * Autodetect onboard SDRAM on 405 platforms
 */
void sdram_init(void)
{
	ulong speed;
	ulong sdtr1;
	int i;

        /*
         * Determine SDRAM speed
         */
        speed = get_bus_freq(0); /* parameter not used on ppc4xx */

        /*
         * sdtr1 (register SDRAM0_TR) must take into account timings listed
         * in SDRAM chip datasheet. rtr (register SDRAM0_RTR) must take into
         * account actual SDRAM size. So we can set up sdtr1 according to what
         * is specified in board configuration file while rtr dependds on SDRAM
         * size we are assuming before detection.
         */
        sdtr1 = compute_sdtr1(speed);

	for (i=0; i<N_MB0CF; i++) {
		/*
		 * Disable memory controller.
		 */
		mtsdram0(mem_mcopt1, 0x00000000);

		/*
		 * Set MB0CF for bank 0.
		 */
		mtsdram0(mem_mb0cf, mb0cf[i].reg);
		mtsdram0(mem_sdtr1, sdtr1);
		mtsdram0(mem_rtr, compute_rtr(speed, mb0cf[i].rows, 64));

		udelay(200);

		/*
		 * Set memory controller options reg, MCOPT1.
		 * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
		 * read/prefetch.
		 */
		mtsdram0(mem_mcopt1, 0x80800000);

		udelay(10000);

		if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
			/*
			 * OK, size detected -> all done
			 */
			return;
		}
	}
}
/*
 * Autodetect onboard SDRAM on 405 platforms
 */
phys_size_t initdram(int board_type)
{
	ulong speed;
	ulong sdtr1;
	int i;

	/*
	 * Determine SDRAM speed
	 */
	speed = get_bus_freq(0); /* parameter not used on ppc4xx */

	/*
	 * sdtr1 (register SDRAM0_TR) must take into account timings listed
	 * in SDRAM chip datasheet. rtr (register SDRAM0_RTR) must take into
	 * account actual SDRAM size. So we can set up sdtr1 according to what
	 * is specified in board configuration file while rtr dependds on SDRAM
	 * size we are assuming before detection.
	 */
	sdtr1 = compute_sdtr1(speed);

	for (i=0; i<N_MB0CF; i++) {
		/*
		 * Disable memory controller.
		 */
		mtsdram(SDRAM0_CFG, 0x00000000);

		/*
		 * Set MB0CF for bank 0.
		 */
		mtsdram(SDRAM0_B0CR, mb0cf[i].reg);
		mtsdram(SDRAM0_TR, sdtr1);
		mtsdram(SDRAM0_RTR, compute_rtr(speed, mb0cf[i].rows, 64));

		udelay(200);

		/*
		 * Set memory controller options reg, MCOPT1.
		 * Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
		 * read/prefetch.
		 */
		mtsdram(SDRAM0_CFG, 0x80800000);

		udelay(10000);

		if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) {
			phys_size_t size = mb0cf[i].size;

			/*
			 * OK, size detected.  Enable second bank if
			 * defined (assumes same type as bank 0)
			 */
#ifdef CONFIG_SDRAM_BANK1
			mtsdram(SDRAM0_CFG, 0x00000000);
			mtsdram(SDRAM0_B1CR, mb0cf[i].size | mb0cf[i].reg);
			mtsdram(SDRAM0_CFG, 0x80800000);
			udelay(10000);

			/*
			 * Check if 2nd bank is really available.
			 * If the size not equal to the size of the first
			 * bank, then disable the 2nd bank completely.
			 */
			if (get_ram_size((long *)mb0cf[i].size, mb0cf[i].size) !=
			    mb0cf[i].size) {
				mtsdram(SDRAM0_B1CR, 0);
				mtsdram(SDRAM0_CFG, 0);
			} else {
				/*
				 * We have two identical banks, so the size
				 * is twice the bank size
				 */
				size = 2 * size;
			}
#endif

			/*
			 * OK, size detected -> all done
			 */
			return size;
		}
	}

	return 0;
}