void Channel::init(int inv, int pin) { //sensibility are used to approximate Time Pulse //usefull on Middle position where there variation of value sensibility = ERROR; //Save Ping of channel if (pin) channelpin = pin; // channelpin[1] = 7, 7 is pin to read Channel 1 //if option inverted are enabled, store config into class Channel if (inv != 1) invert = inv; //init Statics for current Channel ChannelStatistic = Statistic(); ChannelStatistic.clear(); PositionStatistic = Statistic(); PositionStatistic.clear(); //start configuration of Channel clas with output of Reciever configChannel(); }
static void rxfsk (u1_t rxmode) { // only single rx (no continuous scanning, no noise sampling) ASSERT( rxmode == RXMODE_SINGLE ); // select FSK modem (from sleep mode) //writeReg(RegOpMode, 0x00); // (not LoRa) opmodeFSK(); ASSERT((readReg(RegOpMode) & OPMODE_LORA) == 0); // enter standby mode (warm up)) opmode(OPMODE_STANDBY); // configure frequency configChannel(); // set LNA gain //writeReg(RegLna, 0x20|0x03); // max gain, boost enable writeReg(RegLna, LNA_RX_GAIN); // configure receiver writeReg(FSKRegRxConfig, 0x1E); // AFC auto, AGC, trigger on preamble?!? // set receiver bandwidth writeReg(FSKRegRxBw, 0x0B); // 50kHz SSb // set AFC bandwidth writeReg(FSKRegAfcBw, 0x12); // 83.3kHz SSB // set preamble detection writeReg(FSKRegPreambleDetect, 0xAA); // enable, 2 bytes, 10 chip errors // set sync config writeReg(FSKRegSyncConfig, 0x12); // no auto restart, preamble 0xAA, enable, fill FIFO, 3 bytes sync // set packet config writeReg(FSKRegPacketConfig1, 0xD8); // var-length, whitening, crc, no auto-clear, no adr filter writeReg(FSKRegPacketConfig2, 0x40); // packet mode // set sync value writeReg(FSKRegSyncValue1, 0xC1); writeReg(FSKRegSyncValue2, 0x94); writeReg(FSKRegSyncValue3, 0xC1); // set preamble timeout writeReg(FSKRegRxTimeout2, 0xFF);//(LMIC.rxsyms+1)/2); // set bitrate writeReg(FSKRegBitrateMsb, 0x02); // 50kbps writeReg(FSKRegBitrateLsb, 0x80); // set frequency deviation writeReg(FSKRegFdevMsb, 0x01); // +/- 25kHz writeReg(FSKRegFdevLsb, 0x99); // configure DIO mapping DIO0=PayloadReady DIO1=NOP DIO2=TimeOut writeReg(RegDioMapping1, MAP_DIO0_FSK_READY|MAP_DIO1_FSK_NOP|MAP_DIO2_FSK_TIMEOUT); // enable antenna switch for RX hal_pin_rxtx(0); // now instruct the radio to receive hal_waitUntil(LMIC.rxtime); // busy wait until exact rx time opmode(OPMODE_RX); // no single rx mode available in FSK }
// start LoRa receiver (time=LMIC.rxtime, timeout=LMIC.rxsyms, result=LMIC.frame[LMIC.dataLen]) static void rxlora (u1_t rxmode) { // select LoRa modem (from sleep mode) opmodeLora(); ASSERT((readReg(RegOpMode) & OPMODE_LORA) != 0); // enter standby mode (warm up)) opmode(OPMODE_STANDBY); // don't use MAC settings at startup if(rxmode == RXMODE_RSSI) { // use fixed settings for rssi scan writeReg(LORARegModemConfig1, RXLORA_RXMODE_RSSI_REG_MODEM_CONFIG1); writeReg(LORARegModemConfig2, RXLORA_RXMODE_RSSI_REG_MODEM_CONFIG2); } else { // single or continuous rx mode // configure LoRa modem (cfg1, cfg2) configLoraModem(); // configure frequency configChannel(); } // set LNA gain writeReg(RegLna, LNA_RX_GAIN); // set max payload size writeReg(LORARegPayloadMaxLength, 64); // use inverted I/Q signal (prevent mote-to-mote communication) writeReg(LORARegInvertIQ, readReg(LORARegInvertIQ)|(1<<6)); // set symbol timeout (for single rx) writeReg(LORARegSymbTimeoutLsb, LMIC.rxsyms); // set sync word writeReg(LORARegSyncWord, LORA_MAC_PREAMBLE); // configure DIO mapping DIO0=RxDone DIO1=RxTout DIO2=NOP writeReg(RegDioMapping1, MAP_DIO0_LORA_RXDONE|MAP_DIO1_LORA_RXTOUT|MAP_DIO2_LORA_NOP); // clear all radio IRQ flags writeReg(LORARegIrqFlags, 0xFF); // enable required radio IRQs writeReg(LORARegIrqFlagsMask, ~rxlorairqmask[rxmode]); // enable antenna switch for RX hal_pin_rxtx(0); // now instruct the radio to receive if (rxmode == RXMODE_SINGLE) { // single rx hal_waitUntil(LMIC.rxtime); // busy wait until exact rx time opmode(OPMODE_RX_SINGLE); } else { // continous rx (scan or rssi) opmode(OPMODE_RX); } }
static void txfsk () { // select FSK modem (from sleep mode) writeReg(RegOpMode, 0x10); // FSK, BT=0.5 ASSERT(readReg(RegOpMode) == 0x10); // enter standby mode (required for FIFO loading)) opmode(OPMODE_STANDBY); // set bitrate writeReg(FSKRegBitrateMsb, 0x02); // 50kbps writeReg(FSKRegBitrateLsb, 0x80); // set frequency deviation writeReg(FSKRegFdevMsb, 0x01); // +/- 25kHz writeReg(FSKRegFdevLsb, 0x99); // frame and packet handler settings writeReg(FSKRegPreambleMsb, 0x00); writeReg(FSKRegPreambleLsb, 0x05); writeReg(FSKRegSyncConfig, 0x12); writeReg(FSKRegPacketConfig1, 0xD0); writeReg(FSKRegPacketConfig2, 0x40); writeReg(FSKRegSyncValue1, 0xC1); writeReg(FSKRegSyncValue2, 0x94); writeReg(FSKRegSyncValue3, 0xC1); // configure frequency configChannel(); // configure output power configPower(); // set the IRQ mapping DIO0=PacketSent DIO1=NOP DIO2=NOP writeReg(RegDioMapping1, MAP_DIO0_FSK_READY|MAP_DIO1_FSK_NOP|MAP_DIO2_FSK_TXNOP); // initialize the payload size and address pointers writeReg(FSKRegPayloadLength, LMIC.dataLen+1); // (insert length byte into payload)) // download length byte and buffer to the radio FIFO writeReg(RegFifo, LMIC.dataLen); writeBuf(RegFifo, LMIC.frame, LMIC.dataLen); // enable antenna switch for TX hal_pin_rxtx(1); // now we actually start the transmission opmode(OPMODE_TX); }
static void txlora () { // select LoRa modem (from sleep mode) //writeReg(RegOpMode, OPMODE_LORA); opmodeLora(); ASSERT((readReg(RegOpMode) & OPMODE_LORA) != 0); // enter standby mode (required for FIFO loading)) opmode(OPMODE_STANDBY); // configure LoRa modem (cfg1, cfg2) configLoraModem(); // configure frequency configChannel(); // configure output power writeReg(RegPaRamp, (readReg(RegPaRamp) & 0xF0) | 0x08); // set PA ramp-up time 50 uSec configPower(); // set sync word writeReg(LORARegSyncWord, LORA_MAC_PREAMBLE); // set the IRQ mapping DIO0=TxDone DIO1=NOP DIO2=NOP writeReg(RegDioMapping1, MAP_DIO0_LORA_TXDONE|MAP_DIO1_LORA_NOP|MAP_DIO2_LORA_NOP); // clear all radio IRQ flags writeReg(LORARegIrqFlags, 0xFF); // mask all IRQs but TxDone writeReg(LORARegIrqFlagsMask, ~IRQ_LORA_TXDONE_MASK); // initialize the payload size and address pointers writeReg(LORARegFifoTxBaseAddr, 0x00); writeReg(LORARegFifoAddrPtr, 0x00); writeReg(LORARegPayloadLength, LMIC.dataLen); // download buffer to the radio FIFO writeBuf(RegFifo, LMIC.frame, LMIC.dataLen); // enable antenna switch for TX hal_pin_rxtx(1); // now we actually start the transmission opmode(OPMODE_TX); }
bool VideoMixer::configChannelEvent(Jzon::Node* params) { if (!params) { return false; } if (!params->Has("id") || !params->Has("width") || !params->Has("height") || !params->Has("x") || !params->Has("y") || !params->Has("layer") || !params->Has("enabled") || !params->Has("opacity")) { return false; } int id = params->Get("id").ToInt(); float width = params->Get("width").ToFloat(); float height = params->Get("height").ToFloat(); float x = params->Get("x").ToFloat(); float y = params->Get("y").ToFloat(); int layer = params->Get("layer").ToInt(); bool enabled = params->Get("enabled").ToBool(); float opacity = params->Get("opacity").ToFloat(); return configChannel(id, width, height, x, y, layer, enabled, opacity); }