void sdram_init(void)
{
__maybe_unused struct am335x_baseboard_id header;
puts("sdram_init \n");
if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
if (board_is_evm_sk(&header)) {
/*
* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
* This is safe enough to do on older revs.
*/
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
if (board_is_evm_sk(&header))
config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
else if (board_is_bone_lt(&header))
config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
&ddr3_beagleblack_data,
&ddr3_beagleblack_cmd_ctrl_data,
&ddr3_beagleblack_emif_reg_data, 0);
else if (board_is_evm_15_or_later(&header))
config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
else
config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
udelay(500);
}
void sdram_init(void)
{
config_dmm(&evm_lisa_map_regs);
config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
&evm_ddr2_emif0_regs, 0);
config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
&evm_ddr2_emif1_regs, 1);
}
/*
* early system init of muxing and clocks.
*/
void s_init(void)
{
#ifdef CONFIG_SPL_BUILD
/*
* Save the boot parameters passed from romcode.
* We cannot delay the saving further than this,
* to prevent overwrites.
*/
#ifdef CONFIG_SPL_BUILD
save_omap_boot_params();
#endif
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
wdt_disable();
/* Enable timer */
timer_init();
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
/* Enable RTC32K clock */
rtc32k_enable();
/* Set UART pins */
enable_uart0_pin_mux();
/* Set MMC pins */
enable_mmc1_pin_mux();
/* Set Ethernet pins */
enable_enet_pin_mux();
/* Enable UART */
uart_enable();
gd = &gdata;
preloader_console_init();
config_dmm(&evm_lisa_map_regs);
config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
&evm_ddr2_emif0_regs, 0);
config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data,
&evm_ddr2_emif1_regs, 1);
#endif
}
void sdram_init(void)
{
config_ddr(400, &ioregs_bonelt,
&ddr3_sl50_data,
&ddr3_sl50_cmd_ctrl_data,
&ddr3_sl50_emif_reg_data, 0);
}
void sdram_init(void)
{
config_ddr(400, &ioregs_bonelt,
&ddr3_beagleblack_data,
&ddr3_beagleblack_cmd_ctrl_data,
&ddr3_beagleblack_emif_reg_data, 0);
}
/*
* early system init of muxing and clocks.
*/
void s_init(void)
{
/*
* Save the boot parameters passed from romcode.
* We cannot delay the saving further than this,
* to prevent overwrites.
*/
#ifdef CONFIG_SPL_BUILD
save_omap_boot_params();
#endif
/*
* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
writel(0xAAAA, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
writel(0x5555, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
#ifdef CONFIG_SPL_BUILD
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
/* Enable RTC32K clock */
rtc32k_enable();
/* UART softreset */
u32 regval;
enable_uart0_pin_mux();
regval = readl(&uart_base->uartsyscfg);
regval |= UART_RESET;
writel(regval, &uart_base->uartsyscfg);
while ((readl(&uart_base->uartsyssts) & UART_CLK_RUNNING_MASK)
!= UART_CLK_RUNNING_MASK)
;
/* Disable smart idle */
regval = readl(&uart_base->uartsyscfg);
regval |= UART_SMART_IDLE_EN;
writel(regval, &uart_base->uartsyscfg);
gd = &gdata;
preloader_console_init();
/* Initalize the board header */
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
enable_board_pin_mux();
config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
#endif
}
void sdram_init(void)
{
config_ddr(400, &ddr3_ioregs,
&ddr3_data,
&ddr3_cmd_ctrl_data,
&ddr3_emif_reg_data, 0);
}
static void board_init_ddr(void)
{
struct emif_regs dxr2_ddr3_emif_reg_data = {
.zq_config = 0x50074BE4,
};
struct ddr_data dxr2_ddr3_data = {
};
struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
};
/* pass values from eeprom */
dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
dxr2_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
dxr2_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
settings.ddr3.emif_ddr_phy_ctlr_1;
dxr2_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
dxr2_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
dxr2_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
dxr2_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
dxr2_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
dxr2_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
dxr2_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
dxr2_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
dxr2_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
dxr2_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
config_ddr(DDR_PLL_FREQ, settings.ddr3.ioctr_val, &dxr2_ddr3_data,
&dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
}
static void spl_siemens_board_init(void)
{
return;
}
#endif /* if def CONFIG_SPL_BUILD */
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_id = 0,
.phy_if = PHY_INTERFACE_MODE_MII,
},
};
void sdram_init(void)
{
const struct dpll_params *dpll = get_dpll_ddr_params();
/*
* Here we are assuming PLL clock reveals the type of RAM.
* DDR2 = 266
* DDR3 = 400
* Note that DDR3 is the default.
*/
if (dpll->m == 266) {
config_ddr(dpll->m, &ioregs_ddr2, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
}
else if (dpll->m == 400) {
config_ddr(dpll->m, &ioregs_ddr3, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
}
}
void sdram_init(void)
{
unsigned long ram_size;
config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
if (ram_size == 0x80000000 ||
ram_size == 0x40000000 ||
ram_size == 0x20000000)
return;
ddr3_emif_regs.sdram_config = 0x638453B2;
config_ddr(0, &ioregs_ddr3, NULL, NULL, &ddr3_emif_regs, 0);
ram_size = get_ram_size((long int *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
if (ram_size == 0x08000000)
return;
hang();
}
void sdram_init(void)
{
/*
* EPOS EVM has 1GB LPDDR2 connected to EMIF.
* GP EMV has 1GB DDR3 connected to EMIF
* along with VTT regulator.
*/
if (board_is_eposevm()) {
config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
} else if (board_is_evm_14_or_later()) {
enable_vtt_regulator();
config_ddr(0, &ioregs_ddr3, NULL, NULL,
&ddr3_emif_regs_400Mhz_production, 0);
} else if (board_is_evm_12_or_later()) {
enable_vtt_regulator();
config_ddr(0, &ioregs_ddr3, NULL, NULL,
&ddr3_emif_regs_400Mhz_beta, 0);
} else if (board_is_evm()) {
enable_vtt_regulator();
config_ddr(0, &ioregs_ddr3, NULL, NULL,
&ddr3_emif_regs_400Mhz, 0);
} else if (board_is_sk()) {
config_ddr(400, &ioregs_ddr3, NULL, NULL,
&ddr3_sk_emif_regs_400Mhz, 0);
} else if (board_is_idk()) {
config_ddr(400, &ioregs_ddr3, NULL, NULL,
&ddr3_idk_emif_regs_400Mhz, 0);
}
}
static void probe_sdram_size(long size)
{
switch (size) {
case SZ_512M:
ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG;
break;
case SZ_256M:
ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG;
break;
case SZ_128M:
ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG;
break;
default:
puts("Failed configuring DRAM, resetting...\n\n");
reset_cpu(0);
}
debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20);
config_ddr(303, &ioregs, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
}
void sdram_init(void)
{
__maybe_unused struct am335x_baseboard_id header;
if (read_eeprom(&header) < 0)
{
puts("Wrong data in EEEPROM.\n");
hang();
}
if (!board_is_kalitap(&header) &&
!board_is_luna(&header) &&
!board_is_catchwire(&header))
{
puts("Could not get board ID (CatchWire/KaliTAP).\n");
hang();
}
config_ddr(400, &ioregs_catchwire,
&ddr3_catchwire_data,
&ddr3_catchwire_cmd_ctrl_data,
&ddr3_catchwire_emif_reg_data, 0);
puts("Set DDR3 to 800MHz.\n");
}
static void board_init_ddr(void)
{
struct emif_regs pxm2_ddr3_emif_reg_data = {
.sdram_config = 0x41805332,
.sdram_tim1 = 0x666b3c9,
.sdram_tim2 = 0x243631ca,
.sdram_tim3 = 0x33f,
.emif_ddr_phy_ctlr_1 = 0x100005,
.zq_config = 0,
.ref_ctrl = 0x81a,
};
struct ddr_data pxm2_ddr3_data = {
.datardsratio0 = 0x81204812,
.datawdsratio0 = 0,
.datafwsratio0 = 0x8020080,
.datawrsratio0 = 0x4010040,
.datauserank0delay = 1,
.datadldiff0 = PHY_DLL_LOCK_DIFF,
};
struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
.cmd0csratio = 0x80,
.cmd0dldiff = 0,
.cmd0iclkout = 0,
.cmd1csratio = 0x80,
.cmd1dldiff = 0,
.cmd1iclkout = 0,
.cmd2csratio = 0x80,
.cmd2dldiff = 0,
.cmd2iclkout = 0,
};
config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &pxm2_ddr3_data,
&pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0);
}
/*
* voltage switching for MPU frequency switching.
* @module = mpu - 0, core - 1
* @vddx_op_vol_sel = vdd voltage to set
*/
#define MPU 0
#define CORE 1
int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
{
uchar buf[4];
unsigned int reg_offset;
if (module == MPU)
reg_offset = PMIC_VDD1_OP_REG;
else
reg_offset = PMIC_VDD2_OP_REG;
/* Select VDDx OP */
if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
return 1;
buf[0] &= ~PMIC_OP_REG_CMD_MASK;
if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
return 1;
/* Configure VDDx OP Voltage */
if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
return 1;
buf[0] &= ~PMIC_OP_REG_SEL_MASK;
buf[0] |= vddx_op_vol_sel;
if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
return 1;
if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1))
return 1;
if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel)
return 1;
return 0;
}
#define OSC (V_OSCK/1000000)
const struct dpll_params dpll_mpu_pxm2 = {
720, OSC-1, 1, -1, -1, -1, -1};
void spl_siemens_board_init(void)
{
uchar buf[4];
/*
* pxm2 PMIC code. All boards currently want an MPU voltage
* of 1.2625V and CORE voltage of 1.1375V to operate at
* 720MHz.
*/
if (i2c_probe(PMIC_CTRL_I2C_ADDR))
return;
/* VDD1/2 voltage selection register access by control i/f */
if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
return;
buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1))
return;
/* Frequency switching for OPP 120 */
if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) ||
voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) {
printf("voltage update failed\n");
}
}
#endif /* if def CONFIG_SPL_BUILD */
int read_eeprom(void)
{
/* nothing ToDo here for this board */
return 0;
}
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_id = 0,
.phy_if = PHY_INTERFACE_MODE_RMII,
},
{
.slave_reg_ofs = 0x308,
static void board_init_ddr(void)
{
struct emif_regs rut_ddr3_emif_reg_data = {
.sdram_config = 0x61C04AB2,
.sdram_tim1 = 0x0888A39B,
.sdram_tim2 = 0x26337FDA,
.sdram_tim3 = 0x501F830F,
.emif_ddr_phy_ctlr_1 = 0x6,
.zq_config = 0x50074BE4,
.ref_ctrl = 0x93B,
};
struct ddr_data rut_ddr3_data = {
.datardsratio0 = 0x3b,
.datawdsratio0 = 0x85,
.datafwsratio0 = 0x100,
.datawrsratio0 = 0xc1,
};
struct cmd_control rut_ddr3_cmd_ctrl_data = {
.cmd0csratio = 0x40,
.cmd0iclkout = 1,
.cmd1csratio = 0x40,
.cmd1iclkout = 1,
.cmd2csratio = 0x40,
.cmd2iclkout = 1,
};
config_ddr(DDR_PLL_FREQ, RUT_IOCTRL_VAL, &rut_ddr3_data,
&rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
}
static void spl_siemens_board_init(void)
{
return;
}
#endif /* if def CONFIG_SPL_BUILD */
#if defined(CONFIG_DRIVER_TI_CPSW)
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_addr = 1,
.phy_if = PHY_INTERFACE_MODE_RMII,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_addr = 0,
.phy_if = PHY_INTERFACE_MODE_RMII,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
#if defined(CONFIG_DRIVER_TI_CPSW) || \
(defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
int board_eth_init(bd_t *bis)
{
struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
int n = 0;
int rv;
#ifndef CONFIG_SPL_BUILD
factoryset_setenv();
#endif
/* Set rgmii mode and enable rmii clock to be sourced from chip */
writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
rv = cpsw_register(&cpsw_data);
if (rv < 0)
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
return n;
}
#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
#if defined(CONFIG_HW_WATCHDOG)
static bool hw_watchdog_init_done;
static int hw_watchdog_trigger_level;
void hw_watchdog_reset(void)
{
if (!hw_watchdog_init_done)
return;
hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1;
gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
}
void hw_watchdog_init(void)
{
gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger");
gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
hw_watchdog_reset();
hw_watchdog_init_done = 1;
}
#endif /* defined(CONFIG_HW_WATCHDOG) */
#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
static struct da8xx_panel lcd_panels[] = {
/* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
[0] = {
.name = "KWH043MC17-F01",
.width = 480,
.height = 800,
.hfp = 50, /* no spec, "don't care" values */
.hbp = 50,
.hsw = 50,
.vfp = 50,
.vbp = 50,
.vsw = 50,
.pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
.invert_pxl_clk = 1,
},
/*
* early system init of muxing and clocks.
*/
void s_init(void)
{
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
writel(0xAAAA, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
writel(0x5555, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
#ifdef CONFIG_SPL_BUILD
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
/* Enable RTC32K clock */
rtc32k_enable();
/* UART softreset */
u32 regVal;
#ifdef CONFIG_SERIAL1
enable_uart0_pin_mux();
#endif /* CONFIG_SERIAL1 */
#ifdef CONFIG_SERIAL2
enable_uart1_pin_mux();
#endif /* CONFIG_SERIAL2 */
#ifdef CONFIG_SERIAL3
enable_uart2_pin_mux();
#endif /* CONFIG_SERIAL3 */
#ifdef CONFIG_SERIAL4
enable_uart3_pin_mux();
#endif /* CONFIG_SERIAL4 */
#ifdef CONFIG_SERIAL5
enable_uart4_pin_mux();
#endif /* CONFIG_SERIAL5 */
#ifdef CONFIG_SERIAL6
enable_uart5_pin_mux();
#endif /* CONFIG_SERIAL6 */
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_RESET;
writel(regVal, &uart_base->uartsyscfg);
while ((readl(&uart_base->uartsyssts) &
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
;
/* Disable smart idle */
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_SMART_IDLE_EN;
writel(regVal, &uart_base->uartsyscfg);
gd = &gdata;
preloader_console_init();
/* Initalize the board header */
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
enable_board_pin_mux(&header);
if (board_is_evm_sk()) {
/*
* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
* This is safe enough to do on older revs.
*/
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
if (board_is_evm_sk() || board_is_bone_lt())
config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data);
else if (board_is_evm_15_or_later())
config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data);
else
config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data);
#endif
}
void sdram_init(void)
{
config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
}
/*
* early system init of muxing and clocks.
*/
void s_init(void)
{
__maybe_unused struct am335x_baseboard_id header;
#ifdef CONFIG_NOR_BOOT
asm("stmfd sp!, {r2 - r4}");
asm("movw r4, #0x8A4");
asm("movw r3, #0x44E1");
asm("orr r4, r4, r3, lsl #16");
asm("mov r2, #9");
asm("mov r3, #8");
asm("gpmc_mux: str r2, [r4], #4");
asm("subs r3, r3, #1");
asm("bne gpmc_mux");
asm("ldmfd sp!, {r2 - r4}");
#endif
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
writel(0xAAAA, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
writel(0x5555, &wdtimer->wdtwspr);
while (readl(&wdtimer->wdtwwps) != 0x0)
;
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
/* Setup the PLLs and the clocks for the peripherals */
pll_init();
/* Enable RTC32K clock */
rtc32k_enable();
/* UART softreset */
u32 regVal;
enable_uart0_pin_mux();
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_RESET;
writel(regVal, &uart_base->uartsyscfg);
while ((readl(&uart_base->uartsyssts) &
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
;
/* Disable smart idle */
regVal = readl(&uart_base->uartsyscfg);
regVal |= UART_SMART_IDLE_EN;
writel(regVal, &uart_base->uartsyscfg);
#if defined(CONFIG_NOR_BOOT)
/* NOR booting - enable serial console */
gd = (gd_t *) ((CONFIG_SYS_INIT_SP_ADDR) & ~0x07);
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
gd->have_console = 1;
#else
gd = &gdata;
preloader_console_init();
#endif
/* Initalize the board header */
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#ifndef CONFIG_NOR_BOOT
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
#endif
/* Check if baseboard eeprom is available */
if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
puts("Could not probe the EEPROM; something fundamentally "
"wrong on the I2C bus.\n");
}
/* read the eeprom using i2c */
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
sizeof(header))) {
puts("Could not read the EEPROM; something fundamentally"
" wrong on the I2C bus.\n");
}
if (header.magic != 0xEE3355AA) {
/*
* read the eeprom using i2c again,
* but use only a 1 byte address
*/
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
(uchar *)&header, sizeof(header))) {
puts("Could not read the EEPROM; something "
"fundamentally wrong on the I2C bus.\n");
hang();
}
if (header.magic != 0xEE3355AA) {
printf("Incorrect magic number (0x%x) in EEPROM\n",
header.magic);
hang();
}
}
enable_board_pin_mux(&header);
if (!strncmp("A335X_SK", header.name, HDR_NAME_LEN)) {
/*
* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
* This is safe enough to do on older revs.
*/
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}
#ifdef CONFIG_NOR_BOOT
am33xx_spl_board_init();
#endif
/* The following boards are known to use DDR3. */
if ((!strncmp("A335X_SK", header.name, HDR_NAME_LEN)) ||
(!strncmp("A33515BB", header.name, 8) &&
strncmp("1.5", header.version, 3) <= 0))
config_ddr(EMIF_REG_SDRAM_TYPE_DDR3);
else
config_ddr(EMIF_REG_SDRAM_TYPE_DDR2);
#endif
}
void sdram_init(void)
{
config_ddr(266, &ioregs, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
}
static void board_init_ddr(void)
{
struct emif_regs rut_ddr3_emif_reg_data = {
.sdram_config = 0x61C04AB2,
.sdram_tim1 = 0x0888A39B,
.sdram_tim2 = 0x26337FDA,
.sdram_tim3 = 0x501F830F,
.emif_ddr_phy_ctlr_1 = 0x6,
.zq_config = 0x50074BE4,
.ref_ctrl = 0x93B,
};
struct ddr_data rut_ddr3_data = {
.datardsratio0 = 0x3b,
.datawdsratio0 = 0x85,
.datafwsratio0 = 0x100,
.datawrsratio0 = 0xc1,
};
struct cmd_control rut_ddr3_cmd_ctrl_data = {
.cmd0csratio = 0x40,
.cmd0iclkout = 1,
.cmd1csratio = 0x40,
.cmd1iclkout = 1,
.cmd2csratio = 0x40,
.cmd2iclkout = 1,
};
const struct ctrl_ioregs ioregs = {
.cm0ioctl = RUT_IOCTRL_VAL,
.cm1ioctl = RUT_IOCTRL_VAL,
.cm2ioctl = RUT_IOCTRL_VAL,
.dt0ioctl = RUT_IOCTRL_VAL,
.dt1ioctl = RUT_IOCTRL_VAL,
};
config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data,
&rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
}
static int request_and_pulse_reset(int gpio, const char *name)
{
int ret;
const int delay_us = 2000; /* 2ms */
ret = gpio_request(gpio, name);
if (ret < 0) {
printf("%s: Unable to request %s\n", __func__, name);
goto err;
}
ret = gpio_direction_output(gpio, 0);
if (ret < 0) {
printf("%s: Unable to set %s as output\n", __func__, name);
goto err_free_gpio;
}
udelay(delay_us);
gpio_set_value(gpio, 1);
return 0;
err_free_gpio:
gpio_free(gpio);
err:
return ret;
}
#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
#define ETH_PHY_RESET_GPIO GPIO_TO_PIN(2, 18)
#define MAXTOUCH_RESET_GPIO GPIO_TO_PIN(3, 18)
#define DISPLAY_RESET_GPIO GPIO_TO_PIN(3, 19)
#define REQUEST_AND_PULSE_RESET(N) \
request_and_pulse_reset(N, #N);
static void spl_siemens_board_init(void)
{
REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO);
REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO);
REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO);
}
#endif /* if def CONFIG_SPL_BUILD */
#if defined(CONFIG_DRIVER_TI_CPSW)
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_addr = 1,
.phy_if = PHY_INTERFACE_MODE_RMII,
},
{
.slave_reg_ofs = 0x308,
static void board_init_ddr(void)
{
struct emif_regs draco_ddr3_emif_reg_data = {
.zq_config = 0x50074BE4,
};
struct ddr_data draco_ddr3_data = {
};
struct cmd_control draco_ddr3_cmd_ctrl_data = {
};
struct ctrl_ioregs draco_ddr3_ioregs = {
};
/* pass values from eeprom */
draco_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
draco_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2;
draco_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3;
draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
settings.ddr3.emif_ddr_phy_ctlr_1;
draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
draco_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0;
draco_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0;
draco_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0;
draco_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio;
draco_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout;
draco_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio;
draco_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout;
draco_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
draco_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
draco_ddr3_ioregs.cm0ioctl = settings.ddr3.ioctr_val,
draco_ddr3_ioregs.cm1ioctl = settings.ddr3.ioctr_val,
draco_ddr3_ioregs.cm2ioctl = settings.ddr3.ioctr_val,
draco_ddr3_ioregs.dt0ioctl = settings.ddr3.ioctr_val,
draco_ddr3_ioregs.dt1ioctl = settings.ddr3.ioctr_val,
config_ddr(DDR_PLL_FREQ, &draco_ddr3_ioregs, &draco_ddr3_data,
&draco_ddr3_cmd_ctrl_data, &draco_ddr3_emif_reg_data, 0);
}
static void spl_siemens_board_init(void)
{
return;
}
#endif /* if def CONFIG_SPL_BUILD */
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
omap_nand_switch_ecc(1, 8);
#ifdef CONFIG_FACTORYSET
/* Set ASN in environment*/
if (factory_dat.asn[0] != 0) {
setenv("dtb_name", (char *)factory_dat.asn);
} else {
/* dtb suffix gets added in load script */
setenv("dtb_name", "am335x-draco");
}
#else
setenv("dtb_name", "am335x-draco");
#endif
return 0;
}
