void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, const struct dmm_lisa_map_regs *lisa_regs, int nrs) { int i; enable_emif_clocks(); for (i = 0; i < nrs; i++) ddr_init_settings(ctrl, i); enable_dmm_clocks(); /* Program the DMM to for non-interleaved configuration */ config_dmm(lisa_regs); /* Program EMIF CFG Registers */ for (i = 0; i < nrs; i++) { set_sdram_timings(regs, i); config_sdram(regs, i); } udelay(1000); for (i = 0; i < nrs; i++) ddr3_sw_levelling(data, i); udelay(50000); /* Some delay needed */ }
void sdram_init(void) { config_dmm(&evm_lisa_map_regs); config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, &evm_ddr2_emif0_regs, 0); config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, &evm_ddr2_emif1_regs, 1); }
/* * early system init of muxing and clocks. */ void s_init(void) { #ifdef CONFIG_SPL_BUILD /* * Save the boot parameters passed from romcode. * We cannot delay the saving further than this, * to prevent overwrites. */ #ifdef CONFIG_SPL_BUILD save_omap_boot_params(); #endif /* WDT1 is already running when the bootloader gets control * Disable it to avoid "random" resets */ wdt_disable(); /* Enable timer */ timer_init(); /* Setup the PLLs and the clocks for the peripherals */ pll_init(); /* Enable RTC32K clock */ rtc32k_enable(); /* Set UART pins */ enable_uart0_pin_mux(); /* Set MMC pins */ enable_mmc1_pin_mux(); /* Set Ethernet pins */ enable_enet_pin_mux(); /* Enable UART */ uart_enable(); gd = &gdata; preloader_console_init(); config_dmm(&evm_lisa_map_regs); config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, &evm_ddr2_emif0_regs, 0); config_ddr(0, 0, &evm_ddr2_data, &evm_ddr2_cctrl_data, &evm_ddr2_emif1_regs, 1); #endif }