static void local_click_config_provider_wrapper( ButtonId button_id, void* context )
{
if ( config_enabled( button_id, CLICKTYPE_SINGLE ) )
window_single_click_subscribe( button_id, local_click_handler_single ); // single click
if ( config_enabled( button_id, CLICKTYPE_LONG ) )
window_long_click_subscribe( button_id, 0, NULL, local_click_handler_long ); // long click, call on up
if ( config_enabled( button_id, CLICKTYPE_MULTI ) )
window_multi_click_subscribe( button_id, 2, 2, 0, true, local_click_handler_multi ); // double click, call on last
window_set_click_context( button_id, context);
}
static inline void __user *
get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size,
void __user **fpstate)
{
/* Default to using normal stack */
unsigned long math_size = 0;
unsigned long sp = regs->sp;
unsigned long buf_fx = 0;
int onsigstack = on_sig_stack(sp);
/* redzone */
if (config_enabled(CONFIG_X86_64))
sp -= 128;
if (!onsigstack) {
/* This is the X/Open sanctioned signal stack switching. */
if (ka->sa.sa_flags & SA_ONSTACK) {
if (current->sas_ss_size)
sp = current->sas_ss_sp + current->sas_ss_size;
} else if (config_enabled(CONFIG_X86_32) &&
(regs->ss & 0xffff) != __USER_DS &&
#ifdef CONFIG_KERNEL_MODE_LINUX
(regs->sp > TASK_SIZE) &&
#endif
!(ka->sa.sa_flags & SA_RESTORER) &&
ka->sa.sa_restorer) {
/* This is the legacy signal stack switching. */
sp = (unsigned long) ka->sa.sa_restorer;
}
}
if (used_math()) {
sp = alloc_mathframe(sp, config_enabled(CONFIG_X86_32),
&buf_fx, &math_size);
*fpstate = (void __user *)sp;
}
sp = align_sigframe(sp - frame_size);
/*
* If we are on the alternate signal stack and would overflow it, don't.
* Return an always-bogus address instead so we will die with SIGSEGV.
*/
if (onsigstack && !likely(on_sig_stack(sp)))
return (void __user *)-1L;
/* save i387 and extended state */
if (used_math() &&
save_xstate_sig(*fpstate, (void __user *)buf_fx, math_size) < 0)
return (void __user *)-1L;
return (void __user *)sp;
}
void ath9k_cmn_spectral_deinit_debug(struct ath_spec_scan_priv *spec_priv)
{
if (config_enabled(CONFIG_ATH9K_DEBUGFS) && spec_priv->rfs_chan_spec_scan) {
relay_close(spec_priv->rfs_chan_spec_scan);
spec_priv->rfs_chan_spec_scan = NULL;
}
}
void ath9k_cmn_spectral_scan_trigger(struct ath_common *common,
struct ath_spec_scan_priv *spec_priv)
{
struct ath_hw *ah = spec_priv->ah;
u32 rxfilter;
if (config_enabled(CONFIG_ATH9K_TX99))
return;
if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
ath_err(common, "spectrum analyzer not implemented on this hardware\n");
return;
}
ath_ps_ops(common)->wakeup(common);
rxfilter = ath9k_hw_getrxfilter(ah);
ath9k_hw_setrxfilter(ah, rxfilter |
ATH9K_RX_FILTER_PHYRADAR |
ATH9K_RX_FILTER_PHYERR);
/* TODO: usually this should not be neccesary, but for some reason
* (or in some mode?) the trigger must be called after the
* configuration, otherwise the register will have its values reset
* (on my ar9220 to value 0x01002310)
*/
ath9k_cmn_spectral_scan_config(common, spec_priv, spec_priv->spectral_mode);
ath9k_hw_ops(ah)->spectral_scan_trigger(ah);
ath_ps_ops(common)->restore(common);
}
static void http_port_fn(const char *token, char *value, void *UNUSED(setting), FILE *f)
{
if(value)
{
cfg.http_port = 0;
if(value[0])
{
if(value[0] == '+')
{
if(config_enabled(WITH_SSL))
{
cfg.http_use_ssl = 1;
}
else
{
fprintf(stderr, "Warning: OSCam compiled without SSL support.\n");
}
cfg.http_port = strtoul(value + 1, NULL, 10);
}
else
{
cfg.http_port = strtoul(value, NULL, 10);
}
}
return;
}
fprintf_conf(f, token, "%s%d\n", cfg.http_use_ssl ? "+" : "", cfg.http_port);
}
void ath9k_spectral_deinit_debug(struct ath_softc *sc)
{
if (config_enabled(CPTCFG_ATH9K_DEBUGFS) && sc->rfs_chan_spec_scan) {
relay_close(sc->rfs_chan_spec_scan);
sc->rfs_chan_spec_scan = NULL;
}
}
/*
* Prepare the SW reserved portion of the fxsave memory layout, indicating
* the presence of the extended state information in the memory layout
* pointed by the fpstate pointer in the sigcontext.
* This will be saved when ever the FP and extended state context is
* saved on the user stack during the signal handler delivery to the user.
*/
void fpu__init_prepare_fx_sw_frame(void)
{
int size = xstate_size + FP_XSTATE_MAGIC2_SIZE;
fx_sw_reserved.magic1 = FP_XSTATE_MAGIC1;
fx_sw_reserved.extended_size = size;
fx_sw_reserved.xfeatures = xfeatures_mask;
fx_sw_reserved.xstate_size = xstate_size;
if (config_enabled(CONFIG_IA32_EMULATION) ||
config_enabled(CONFIG_X86_32)) {
int fsave_header_size = sizeof(struct fregs_state);
fx_sw_reserved_ia32 = fx_sw_reserved;
fx_sw_reserved_ia32.extended_size = size + fsave_header_size;
}
}
static bool ath_reg_dyn_country_user_allow(struct ath_regulatory *reg)
{
if (!config_enabled(CPTCFG_ATH_REG_DYNAMIC_USER_REG_HINTS))
return false;
if (!dynamic_country_user_possible(reg))
return false;
return true;
}
/*
* APIC command line parameters
*/
static int __init parse_lapic(char *arg)
{
if (config_enabled(CONFIG_X86_32) && !arg)
force_enable_local_apic = 1;
else if (arg && !strncmp(arg, "notscdeadline", 13))
setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
return 0;
}
/*
* Prepare the SW reserved portion of the fxsave memory layout, indicating
* the presence of the extended state information in the memory layout
* pointed by the fpstate pointer in the sigcontext.
* This will be saved when ever the FP and extended state context is
* saved on the user stack during the signal handler delivery to the user.
*/
static void prepare_fx_sw_frame(void)
{
int size = xstate_size + FP_XSTATE_MAGIC2_SIZE;
fx_sw_reserved.magic1 = FP_XSTATE_MAGIC1;
fx_sw_reserved.extended_size = size;
fx_sw_reserved.xstate_bv = pcntxt_mask;
fx_sw_reserved.xstate_size = xstate_size;
if (config_enabled(CONFIG_IA32_EMULATION) ||
config_enabled(CONFIG_X86_32)) {
int fsave_header_size = sizeof(struct i387_fsave_struct);
fx_sw_reserved_ia32 = fx_sw_reserved;
fx_sw_reserved_ia32.extended_size = size + fsave_header_size;
}
}
int restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sc)
{
unsigned long buf_val;
void __user *buf;
unsigned int tmpflags;
unsigned int err = 0;
/* Always make any pending restarted system calls return -EINTR */
current->restart_block.fn = do_no_restart_syscall;
get_user_try {
#ifdef CONFIG_X86_32
set_user_gs(regs, GET_SEG(gs));
COPY_SEG(fs);
COPY_SEG(es);
COPY_SEG(ds);
#endif /* CONFIG_X86_32 */
COPY(di); COPY(si); COPY(bp); COPY(sp); COPY(bx);
COPY(dx); COPY(cx); COPY(ip); COPY(ax);
#ifdef CONFIG_X86_64
COPY(r8);
COPY(r9);
COPY(r10);
COPY(r11);
COPY(r12);
COPY(r13);
COPY(r14);
COPY(r15);
#endif /* CONFIG_X86_64 */
#ifdef CONFIG_X86_32
COPY_SEG_CPL3(cs);
COPY_SEG_CPL3(ss);
#else /* !CONFIG_X86_32 */
/* Kernel saves and restores only the CS segment register on signals,
* which is the bare minimum needed to allow mixed 32/64-bit code.
* App's signal handler can save/restore other segments if needed. */
COPY_SEG_CPL3(cs);
#endif /* CONFIG_X86_32 */
get_user_ex(tmpflags, &sc->flags);
regs->flags = (regs->flags & ~FIX_EFLAGS) | (tmpflags & FIX_EFLAGS);
regs->orig_ax = -1; /* disable syscall checks */
get_user_ex(buf_val, &sc->fpstate);
buf = (void __user *)buf_val;
} get_user_catch(err);
err |= fpu__restore_sig(buf, config_enabled(CONFIG_X86_32));
force_iret();
return err;
}
int mips_cm_probe(void)
{
phys_addr_t addr;
u32 base_reg;
unsigned cpu;
/*
* No need to probe again if we have already been
* here before.
*/
if (mips_cm_base)
return 0;
addr = mips_cm_phys_base();
BUG_ON((addr & CM_GCR_BASE_GCRBASE_MSK) != addr);
if (!addr)
return -ENODEV;
mips_cm_base = ioremap_nocache(addr, MIPS_CM_GCR_SIZE);
if (!mips_cm_base)
return -ENXIO;
/* sanity check that we're looking at a CM */
base_reg = read_gcr_base();
if ((base_reg & CM_GCR_BASE_GCRBASE_MSK) != addr) {
pr_err("GCRs appear to have been moved (expected them at 0x%08lx)!\n",
(unsigned long)addr);
mips_cm_base = NULL;
return -ENODEV;
}
/* set default target to memory */
base_reg &= ~CM_GCR_BASE_CMDEFTGT_MSK;
base_reg |= CM_GCR_BASE_CMDEFTGT_MEM;
write_gcr_base(base_reg);
/* disable CM regions */
write_gcr_reg0_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
write_gcr_reg0_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
write_gcr_reg1_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
write_gcr_reg1_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
write_gcr_reg2_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
write_gcr_reg2_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
write_gcr_reg3_base(CM_GCR_REGn_BASE_BASEADDR_MSK);
write_gcr_reg3_mask(CM_GCR_REGn_MASK_ADDRMASK_MSK);
/* probe for an L2-only sync region */
mips_cm_probe_l2sync();
/* determine register width for this CM */
mips_cm_is64 = config_enabled(CONFIG_64BIT) && (mips_cm_revision() >= CM_REV_CM3);
for_each_possible_cpu(cpu)
spin_lock_init(&per_cpu(cm_core_lock, cpu));
return 0;
}
/*
* Save the fpu, extended register state to the user signal frame.
*
* 'buf_fx' is the 64-byte aligned pointer at which the [f|fx|x]save
* state is copied.
* 'buf' points to the 'buf_fx' or to the fsave header followed by 'buf_fx'.
*
* buf == buf_fx for 64-bit frames and 32-bit fsave frame.
* buf != buf_fx for 32-bit frames with fxstate.
*
* If the fpu, extended register state is live, save the state directly
* to the user frame pointed by the aligned pointer 'buf_fx'. Otherwise,
* copy the thread's fpu state to the user frame starting at 'buf_fx'.
*
* If this is a 32-bit frame with fxstate, put a fsave header before
* the aligned state at 'buf_fx'.
*
* For [f]xsave state, update the SW reserved fields in the [f]xsave frame
* indicating the absence/presence of the extended state to the user.
*/
int save_xstate_sig(void __user *buf, void __user *buf_fx, int size)
{
struct xsave_struct *xsave = ¤t->thread.fpu.state->xsave;
struct task_struct *tsk = current;
int ia32_fxstate = (buf != buf_fx);
ia32_fxstate &= (config_enabled(CONFIG_X86_32) ||
config_enabled(CONFIG_IA32_EMULATION));
if (!access_ok(VERIFY_WRITE, buf, size))
return -EACCES;
if (!static_cpu_has(X86_FEATURE_FPU))
return fpregs_soft_get(current, NULL, 0,
sizeof(struct user_i387_ia32_struct), NULL,
(struct _fpstate_ia32 __user *) buf) ? -1 : 1;
if (!config_enabled(CONFIG_L4) && user_has_fpu()) {
/* Save the live register state to the user directly. */
if (save_user_xstate(buf_fx))
return -1;
/* Update the thread's fxstate to save the fsave header. */
if (ia32_fxstate)
fpu_fxsave(&tsk->thread.fpu);
} else {
if (config_enabled(CONFIG_L4) && user_has_fpu())
unlazy_fpu(tsk);
sanitize_i387_state(tsk);
if (__copy_to_user(buf_fx, xsave, xstate_size))
return -1;
}
/* Save the fsave header for the 32-bit frames. */
if ((ia32_fxstate || !use_fxsr()) && save_fsave_header(tsk, buf))
return -1;
if (use_fxsr() && save_xstate_epilog(buf_fx, ia32_fxstate))
return -1;
drop_init_fpu(tsk); /* trigger finit */
return 0;
}
void __init fw_meminit(void)
{
fw_memblock_t *p;
p = fw_getmdesc(config_enabled(CONFIG_EVA));
free_init_pages_eva = (config_enabled(CONFIG_EVA) ?
free_init_pages_eva_malta : NULL);
while (p->size) {
long type;
unsigned long base, size;
type = fw_memtype_classify(p->type);
base = p->base;
size = p->size;
add_memory_region(base, size, type);
p++;
}
}
static unsigned core_vpe_count(unsigned core)
{
unsigned cfg;
if (!config_enabled(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
return 1;
write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF);
cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
}
static unsigned core_vpe_count(unsigned core)
{
unsigned cfg;
if (!config_enabled(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
return 1;
mips_cm_lock_other(core, 0);
cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
mips_cm_unlock_other();
return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
}
int ath10k_thermal_register(struct ath10k *ar)
{
struct thermal_cooling_device *cdev;
struct device *hwmon_dev;
int ret;
cdev = thermal_cooling_device_register("ath10k_thermal", ar,
&ath10k_thermal_ops);
if (IS_ERR(cdev)) {
ath10k_err(ar, "failed to setup thermal device result: %ld\n",
PTR_ERR(cdev));
return -EINVAL;
}
ret = sysfs_create_link(&ar->dev->kobj, &cdev->device.kobj,
"cooling_device");
if (ret) {
ath10k_err(ar, "failed to create cooling device symlink\n");
goto err_cooling_destroy;
}
ar->thermal.cdev = cdev;
ar->thermal.quiet_period = ATH10K_QUIET_PERIOD_DEFAULT;
/* Do not register hwmon device when temperature reading is not
* supported by firmware
*/
if (ar->wmi.op_version != ATH10K_FW_WMI_OP_VERSION_10_2_4)
return 0;
/* Avoid linking error on devm_hwmon_device_register_with_groups, I
* guess linux/hwmon.h is missing proper stubs. */
if (!config_enabled(CONFIG_HWMON))
return 0;
hwmon_dev = devm_hwmon_device_register_with_groups(ar->dev,
"ath10k_hwmon", ar,
ath10k_hwmon_groups);
if (IS_ERR(hwmon_dev)) {
ath10k_err(ar, "failed to register hwmon device: %ld\n",
PTR_ERR(hwmon_dev));
ret = -EINVAL;
goto err_remove_link;
}
return 0;
err_remove_link:
sysfs_remove_link(&ar->dev->kobj, "cooling_device");
err_cooling_destroy:
thermal_cooling_device_unregister(cdev);
return ret;
}
static inline unsigned long dcache_line_size(void)
{
unsigned long conf1, dl;
if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
return CONFIG_SYS_DCACHE_LINE_SIZE;
conf1 = read_c0_config1();
dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
if (!dl)
return 0;
return 2 << dl;
}
static inline unsigned long icache_line_size(void)
{
unsigned long conf1, il;
if (!config_enabled(CONFIG_SYS_CACHE_SIZE_AUTO))
return CONFIG_SYS_ICACHE_LINE_SIZE;
conf1 = read_c0_config1();
il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
if (!il)
return 0;
return 2 << il;
}
int ath10k_debug_create(struct ath10k *ar)
{
ar->debug.debugfs_phy = debugfs_create_dir("ath10k",
ar->hw->wiphy->debugfsdir);
if (!ar->debug.debugfs_phy)
return -ENOMEM;
INIT_DELAYED_WORK(&ar->debug.htt_stats_dwork,
ath10k_debug_htt_stats_dwork);
init_completion(&ar->debug.event_stats_compl);
debugfs_create_file("fw_stats", S_IRUSR, ar->debug.debugfs_phy, ar,
&fops_fw_stats);
debugfs_create_file("wmi_services", S_IRUSR, ar->debug.debugfs_phy, ar,
&fops_wmi_services);
debugfs_create_file("simulate_fw_crash", S_IRUSR, ar->debug.debugfs_phy,
ar, &fops_simulate_fw_crash);
debugfs_create_file("chip_id", S_IRUSR, ar->debug.debugfs_phy,
ar, &fops_chip_id);
debugfs_create_file("htt_stats_mask", S_IRUSR, ar->debug.debugfs_phy,
ar, &fops_htt_stats_mask);
debugfs_create_file("htt_max_amsdu_ampdu", S_IRUSR | S_IWUSR,
ar->debug.debugfs_phy, ar,
&fops_htt_max_amsdu_ampdu);
debugfs_create_file("fw_dbglog", S_IRUSR, ar->debug.debugfs_phy,
ar, &fops_fw_dbglog);
if (config_enabled(CONFIG_ATH10K_DFS_CERTIFIED)) {
debugfs_create_file("dfs_simulate_radar", S_IWUSR,
ar->debug.debugfs_phy, ar,
&fops_simulate_radar);
debugfs_create_bool("dfs_block_radar_events", S_IWUSR,
ar->debug.debugfs_phy,
&ar->dfs_block_radar_events);
debugfs_create_file("dfs_stats", S_IRUSR,
ar->debug.debugfs_phy, ar,
&fops_dfs_stats);
}
return 0;
}
void
ath10k_print_driver_info(struct ath10k *ar)
{
char fw_features[128] = {};
ath10k_core_get_fw_features_str(ar, fw_features, sizeof(fw_features));
device_printf(ar->sc_dev,
"%s (0x%08x, 0x%08x%s%s%s) fw %s api %d htt-ver %d.%d wmi-op %d htt-op %d cal %s max-sta %d raw %d hwcrypto %d features %s\n",
ar->hw_params.name,
ar->target_version,
ar->sc_chipid,
(strlen(ar->spec_board_id) > 0 ? ", " : ""),
ar->spec_board_id,
(strlen(ar->spec_board_id) > 0 && !ar->spec_board_loaded
? " fallback" : ""),
ar->fw_version_str,
ar->fw_api,
ar->htt.target_version_major,
ar->htt.target_version_minor,
ar->wmi.op_version,
ar->htt.op_version,
ath10k_cal_mode_str(ar->cal_mode),
ar->max_num_stations,
(int) test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags),
(int) !test_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags),
fw_features);
#if 0
device_printf(ar->sc_dev,
"debug %d debugfs %d tracing %d dfs %d testmode %d\n",
config_enabled(CONFIG_ATH10K_DEBUG),
config_enabled(CONFIG_ATH10K_DEBUGFS),
config_enabled(CONFIG_ATH10K_TRACING),
config_enabled(CONFIG_ATH10K_DFS_CERTIFIED),
config_enabled(CONFIG_NL80211_TESTMODE));
#endif
}
/*
* Migrate the IO-APIC irq in the presence of intr-remapping.
*
* For both level and edge triggered, irq migration is a simple atomic
* update(of vector and cpu destination) of IRTE and flush the hardware cache.
*
* For level triggered, we eliminate the io-apic RTE modification (with the
* updated vector information), by using a virtual vector (io-apic pin number).
* Real vector that is used for interrupting cpu will be coming from
* the interrupt-remapping table entry.
*
* As the migration is a simple atomic update of IRTE, the same mechanism
* is used to migrate MSI irq's in the presence of interrupt-remapping.
*/
static int
intel_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
bool force)
{
struct irq_cfg *cfg = data->chip_data;
unsigned int dest, irq = data->irq;
struct irte irte;
int err;
if (!config_enabled(CONFIG_SMP))
return -EINVAL;
if (!cpumask_intersects(mask, cpu_online_mask))
return -EINVAL;
if (get_irte(irq, &irte))
return -EBUSY;
err = assign_irq_vector(irq, cfg, mask);
if (err)
return err;
err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest);
if (err) {
if (assign_irq_vector(irq, cfg, data->affinity))
pr_err("Failed to recover vector for irq %d\n", irq);
return err;
}
irte.vector = cfg->vector;
irte.dest_id = IRTE_DEST(dest);
/*
* Atomically updates the IRTE with the new destination, vector
* and flushes the interrupt entry cache.
*/
modify_irte(irq, &irte);
/*
* After this point, all the interrupts will start arriving
* at the new destination. So, time to cleanup the previous
* vector allocation.
*/
if (cfg->move_in_progress)
send_cleanup_vector(cfg);
cpumask_copy(data->affinity, mask);
return 0;
}
static void do_report_emm_support(void) {
if (!config_enabled(WITH_CARDREADER)) {
cs_log("Binary without Cardreader Support! No EMM processing possible!");
} else {
report_emm_support(READER_NAGRA, "Nagra");
report_emm_support(READER_IRDETO, "Irdeto");
report_emm_support(READER_CONAX, "Conax");
report_emm_support(READER_CRYPTOWORKS, "Cryptoworks");
report_emm_support(READER_SECA, "Seca");
report_emm_support(READER_VIACCESS, "Viaccess");
report_emm_support(READER_VIDEOGUARD, "NDS Videoguard");
report_emm_support(READER_DRE, "DRE Crypt");
report_emm_support(READER_TONGFANG, "TONGFANG");
report_emm_support(READER_BULCRYPT, "Bulcrypt");
report_emm_support(READER_GRIFFIN, "Griffin");
report_emm_support(READER_DGCRYPT, "DGCrypt");
}
}
static ssize_t write_file_spec_scan_ctl(struct file *file,
const char __user *user_buf,
size_t count, loff_t *ppos)
{
struct ath_softc *sc = file->private_data;
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
char buf[32];
ssize_t len;
if (config_enabled(CPTCFG_ATH9K_TX99))
return -EOPNOTSUPP;
len = min(count, sizeof(buf) - 1);
if (copy_from_user(buf, user_buf, len))
return -EFAULT;
buf[len] = '\0';
if (strncmp("trigger", buf, 7) == 0) {
ath9k_spectral_scan_trigger(sc->hw);
} else if (strncmp("background", buf, 9) == 0) {
ath9k_spectral_scan_config(sc->hw, SPECTRAL_BACKGROUND);
ath_dbg(common, CONFIG, "spectral scan: background mode enabled\n");
} else if (strncmp("chanscan", buf, 8) == 0) {
ath9k_spectral_scan_config(sc->hw, SPECTRAL_CHANSCAN);
ath_dbg(common, CONFIG, "spectral scan: channel scan mode enabled\n");
} else if (strncmp("manual", buf, 6) == 0) {
ath9k_spectral_scan_config(sc->hw, SPECTRAL_MANUAL);
ath_dbg(common, CONFIG, "spectral scan: manual mode enabled\n");
} else if (strncmp("disable", buf, 7) == 0) {
ath9k_spectral_scan_config(sc->hw, SPECTRAL_DISABLED);
ath_dbg(common, CONFIG, "spectral scan: disabled\n");
} else {
return -EINVAL;
}
return count;
}
/* Prints usage information and information about the built-in modules. */
static void show_usage(void)
{
printf("%s",
" ___ ____ ___\n"
" / _ \\/ ___| / __|__ _ _ __ ___\n"
"| | | \\___ \\| | / _` | '_ ` _ \\\n"
"| |_| |___) | |_| (_| | | | | | |\n"
" \\___/|____/ \\___\\__,_|_| |_| |_|\n\n");
printf("OSCam cardserver v%s, build r%s (%s)\n", CS_VERSION, CS_SVN_VERSION, CS_TARGET);
printf("Copyright (C) 2009-2013 OSCam developers.\n");
printf("This program is distributed under GPLv3.\n");
printf("OSCam is based on Streamboard mp-cardserver v0.9d written by dukat\n");
printf("Visit http://www.streamboard.tv/oscam/ for more details.\n\n");
printf(" ConfigDir : %s\n", CS_CONFDIR);
printf("\n");
printf(" Usage: oscam [parameters]\n");
printf("\n Directories:\n");
printf(" -c, --config-dir <dir> | Read configuration files from <dir>.\n");
printf(" . Default: %s\n", CS_CONFDIR);
printf(" -t, --temp-dir <dir> | Set temporary directory to <dir>.\n");
#if defined(__CYGWIN__)
printf(" . Default: (OS-TMP)\n");
#else
printf(" . Default: /tmp/.oscam\n");
#endif
printf("\n Startup:\n");
printf(" -b, --daemon | Start in the background as daemon.\n");
printf(" -B, --pidfile <pidfile> | Create pidfile when starting.\n");
if (config_enabled(WEBIF)) {
printf(" -r, --restart <level> | Set restart level:\n");
printf(" . 0 - Restart disabled (exit on restart request).\n");
printf(" . 1 - WebIf restart is active (default).\n");
printf(" . 2 - Like 1, but also restart on segfaults.\n");
}
printf(" -w, --wait <secs> | Set how much seconds to wait at startup for the\n");
printf(" . system clock to be set correctly. Default: 60\n");
printf("\n Logging:\n");
printf(" -I, --syslog-ident <ident> | Set syslog ident. Default: oscam\n");
printf(" -S, --show-sensitive | Do not filter sensitive info (card serials, boxids)\n");
printf(" . from the logs.\n");
printf(" -d, --debug <level> | Set debug level mask used for logging:\n");
printf(" . 0 - No extra debugging (default).\n");
printf(" . 1 - Detailed error messages.\n");
printf(" . 2 - ATR parsing info, ECM, EMM and CW dumps.\n");
printf(" . 4 - Traffic from/to the reader.\n");
printf(" . 8 - Traffic from/to the clients.\n");
printf(" . 16 - Traffic to the reader-device on IFD layer.\n");
printf(" . 32 - Traffic to the reader-device on I/O layer.\n");
printf(" . 64 - EMM logging.\n");
printf(" . 128 - DVBAPI logging.\n");
printf(" . 256 - Loadbalancer logging.\n");
printf(" . 512 - CACHEEX logging.\n");
printf(" . 1024 - Client ECM logging.\n");
printf(" . 65535 - Debug all.\n");
printf("\n Settings:\n");
printf(" -p, --pending-ecm <num> | Set the maximum number of pending ECM packets.\n");
printf(" . Default: 32 Max: 255\n");
if (config_enabled(WEBIF)) {
printf(" -u, --utf8 | Enable WebIf support for UTF-8 charset.\n");
}
printf("\n Debug parameters:\n");
printf(" -a, --crash-dump | Write oscam.crash file on segfault. This option\n");
printf(" . needs GDB to be installed and OSCam executable to\n");
printf(" . contain the debug information (run oscam-XXXX.debug)\n");
printf(" -s, --capture-segfaults | Capture segmentation faults.\n");
printf(" -g, --gcollect <mode> | Garbage collector debug mode:\n");
printf(" . 1 - Immediate free.\n");
printf(" . 2 - Check for double frees.\n");
printf("\n Information:\n");
printf(" -h, --help | Show command line help text.\n");
printf(" -V, --build-info | Show OSCam binary configuration and version.\n");
}
static void write_versionfile(bool use_stdout) {
FILE *fp = stdout;
if (!use_stdout) {
char targetfile[256];
fp = fopen(get_tmp_dir_filename(targetfile, sizeof(targetfile), "oscam.version"), "w");
if (!fp) {
cs_log("Cannot open %s (errno=%d %s)", targetfile, errno, strerror(errno));
return;
}
struct tm st;
time_t now = time(NULL);
localtime_r(&now, &st);
fprintf(fp, "Unix starttime: %ld\n", (long)now);
fprintf(fp, "Starttime: %02d.%02d.%04d %02d:%02d:%02d\n",
st.tm_mday, st.tm_mon + 1, st.tm_year + 1900,
st.tm_hour, st.tm_min, st.tm_sec);
}
fprintf(fp, "Version: oscam-%s-r%s\n", CS_VERSION, CS_SVN_VERSION);
fprintf(fp, "\n");
write_conf(WEBIF, "Web interface support");
write_conf(TOUCH, "Touch interface support");
write_conf(WITH_SSL, "SSL support");
write_conf(HAVE_DVBAPI, "DVB API support");
if (config_enabled(HAVE_DVBAPI)) {
write_conf(WITH_AZBOX, "DVB API with AZBOX support");
write_conf(WITH_MCA, "DVB API with MCA support");
write_conf(WITH_COOLAPI, "DVB API with COOLAPI support");
write_conf(WITH_STAPI, "DVB API with STAPI support");
}
write_conf(CS_ANTICASC, "Anti-cascading support");
write_conf(IRDETO_GUESSING, "Irdeto guessing");
write_conf(WITH_DEBUG, "Debug mode");
write_conf(MODULE_MONITOR, "Monitor");
write_conf(WITH_LB, "Loadbalancing support");
write_conf(CW_CYCLE_CHECK, "CW Cycle Check support");
write_conf(LCDSUPPORT, "LCD support");
write_conf(LEDSUPPORT, "LED support");
write_conf(IPV6SUPPORT, "IPv6 support");
write_conf(CS_CACHEEX, "Cache exchange support");
fprintf(fp, "\n");
write_conf(MODULE_CAMD33, "camd 3.3x");
write_conf(MODULE_CAMD35, "camd 3.5 UDP");
write_conf(MODULE_CAMD35_TCP, "camd 3.5 TCP");
write_conf(MODULE_NEWCAMD, "newcamd");
write_conf(MODULE_CCCAM, "CCcam");
write_conf(MODULE_CCCSHARE, "CCcam share");
write_conf(MODULE_PANDORA, "Pandora");
write_conf(MODULE_GHTTP, "ghttp");
write_conf(MODULE_GBOX, "gbox");
write_conf(MODULE_RADEGAST, "radegast");
write_conf(MODULE_SERIAL, "serial");
write_conf(MODULE_CONSTCW, "constant CW");
fprintf(fp, "\n");
write_conf(WITH_CARDREADER, "Reader support");
if (config_enabled(WITH_CARDREADER)) {
fprintf(fp, "\n");
write_readerconf(READER_NAGRA, "Nagra");
write_readerconf(READER_IRDETO, "Irdeto");
write_readerconf(READER_CONAX, "Conax");
write_readerconf(READER_CRYPTOWORKS, "Cryptoworks");
write_readerconf(READER_SECA, "Seca");
write_readerconf(READER_VIACCESS, "Viaccess");
write_readerconf(READER_VIDEOGUARD, "NDS Videoguard");
write_readerconf(READER_DRE, "DRE Crypt");
write_readerconf(READER_TONGFANG, "TONGFANG");
write_readerconf(READER_BULCRYPT, "Bulcrypt");
write_readerconf(READER_GRIFFIN, "Griffin");
write_readerconf(READER_DGCRYPT, "DGCrypt");
fprintf(fp, "\n");
write_cardreaderconf(CARDREADER_PHOENIX, "phoenix");
write_cardreaderconf(CARDREADER_INTERNAL_AZBOX, "internal_azbox");
write_cardreaderconf(CARDREADER_INTERNAL_COOLAPI, "internal_coolapi");
write_cardreaderconf(CARDREADER_INTERNAL_SCI, "internal_sci");
write_cardreaderconf(CARDREADER_SC8IN1, "sc8in1");
write_cardreaderconf(CARDREADER_MP35, "mp35");
write_cardreaderconf(CARDREADER_SMARGO, "smargo");
write_cardreaderconf(CARDREADER_PCSC, "pcsc");
write_cardreaderconf(CARDREADER_SMART, "smartreader");
write_cardreaderconf(CARDREADER_DB2COM, "db2com");
write_cardreaderconf(CARDREADER_STAPI, "stapi");
} else {
write_readerconf(WITH_CARDREADER, "Reader Support");
}
if (!use_stdout)
fclose(fp);
}
static void parse_cmdline_params(int argc, char **argv) {
int i;
while ((i = getopt_long(argc, argv, short_options, long_options, NULL)) != EOF) {
if (i == '?')
fprintf(stderr, "ERROR: Unknown command line parameter: %s\n", argv[optind - 1]);
switch(i) {
case 'a': // --crash-dump
cs_dump_stack = 1;
break;
case 'B': // --pidfile
oscam_pidfile = optarg;
break;
case 'b': // --daemon
bg = 1;
break;
case 'c': // --config-dir
cs_strncpy(cs_confdir, optarg, sizeof(cs_confdir));
break;
case 'd': // --debug
cs_dblevel = atoi(optarg);
break;
case 'g': // --gcollect
gbdb = atoi(optarg);
break;
case 'h': // --help
show_usage();
exit(EXIT_SUCCESS);
break;
case 'I': // --syslog-ident
syslog_ident = optarg;
break;
case 'p': // --pending-ecm
max_pending = atoi(optarg) <= 0 ? 32 : MIN(atoi(optarg), 255);
break;
case 'r': // --restart
if (config_enabled(WEBIF)) {
cs_restart_mode = atoi(optarg);
}
break;
case 'S': // --show-sensitive
log_remove_sensitive = !log_remove_sensitive;
break;
case 's': // --capture-segfaults
cs_capture_SEGV = 1;
break;
case 't': { // --temp-dir
mkdir(optarg, S_IRWXU);
int j = open(optarg, O_RDONLY);
if (j >= 0) {
close(j);
cs_strncpy(cs_tmpdir, optarg, sizeof(cs_tmpdir));
} else {
printf("WARNING: Temp dir does not exist. Using default value.\n");
}
break;
}
case 'u': // --utf8
if (config_enabled(WEBIF)) {
cs_http_use_utf8 = 1;
printf("WARNING: Web interface UTF-8 mode enabled. Carefully read documentation as bugs may arise.\n");
}
break;
case 'V': // --build-info
write_versionfile(true);
exit(EXIT_SUCCESS);
break;
case 'w': // --wait
cs_waittime = strtoul(optarg, NULL, 10);
break;
}
}
}
static inline bool ar933x_uart_console_enabled(void)
{
return config_enabled(CONFIG_SERIAL_AR933X_CONSOLE);
}
int __restore_xstate_sig(void __user *buf, void __user *buf_fx, int size)
{
int ia32_fxstate = (buf != buf_fx);
struct task_struct *tsk = current;
int state_size = xstate_size;
u64 xstate_bv = 0;
int fx_only = 0;
ia32_fxstate &= (config_enabled(CONFIG_X86_32) ||
config_enabled(CONFIG_IA32_EMULATION));
if (!buf) {
drop_init_fpu(tsk);
return 0;
}
if (!access_ok(VERIFY_READ, buf, size))
return -EACCES;
if (!used_math() && init_fpu(tsk))
return -1;
if (!static_cpu_has(X86_FEATURE_FPU))
return fpregs_soft_set(current, NULL,
0, sizeof(struct user_i387_ia32_struct),
NULL, buf) != 0;
if (use_xsave()) {
struct _fpx_sw_bytes fx_sw_user;
if (unlikely(check_for_xstate(buf_fx, buf_fx, &fx_sw_user))) {
/*
* Couldn't find the extended state information in the
* memory layout. Restore just the FP/SSE and init all
* the other extended state.
*/
state_size = sizeof(struct i387_fxsave_struct);
fx_only = 1;
} else {
state_size = fx_sw_user.xstate_size;
xstate_bv = fx_sw_user.xstate_bv;
}
}
if (ia32_fxstate) {
/*
* For 32-bit frames with fxstate, copy the user state to the
* thread's fpu state, reconstruct fxstate from the fsave
* header. Sanitize the copied state etc.
*/
struct xsave_struct *xsave = &tsk->thread.fpu.state->xsave;
struct user_i387_ia32_struct env;
int err = 0;
/*
* Drop the current fpu which clears used_math(). This ensures
* that any context-switch during the copy of the new state,
* avoids the intermediate state from getting restored/saved.
* Thus avoiding the new restored state from getting corrupted.
* We will be ready to restore/save the state only after
* set_used_math() is again set.
*/
drop_fpu(tsk);
if (__copy_from_user(xsave, buf_fx, state_size) ||
__copy_from_user(&env, buf, sizeof(env))) {
err = -1;
} else {
sanitize_restored_xstate(tsk, &env, xstate_bv, fx_only);
set_used_math();
}
if (use_eager_fpu())
math_state_restore();
return err;
} else {
/*
* For 64-bit frames and 32-bit fsave frames, restore the user
* state to the registers directly (with exceptions handled).
*/
user_fpu_begin();
if (restore_user_xstate(buf_fx, xstate_bv, fx_only)) {
drop_init_fpu(tsk);
return -1;
}
}
return 0;
}
static int __fpu__restore_sig(void __user *buf, void __user *buf_fx, int size)
{
int ia32_fxstate = (buf != buf_fx);
struct task_struct *tsk = current;
struct fpu *fpu = &tsk->thread.fpu;
int state_size = xstate_size;
u64 xfeatures = 0;
int fx_only = 0;
ia32_fxstate &= (config_enabled(CONFIG_X86_32) ||
config_enabled(CONFIG_IA32_EMULATION));
#ifdef CONFIG_L4
/* use the ia32_fxstate path all the time,
* otherwise we have direct access to user mappings */
ia32_fxstate |= config_enabled(CONFIG_L4);
#endif /* L4 */
if (!buf) {
fpu__clear(fpu);
return 0;
}
if (!access_ok(VERIFY_READ, buf, size))
return -EACCES;
fpu__activate_curr(fpu);
if (!static_cpu_has(X86_FEATURE_FPU))
return fpregs_soft_set(current, NULL,
0, sizeof(struct user_i387_ia32_struct),
NULL, buf) != 0;
if (use_xsave()) {
struct _fpx_sw_bytes fx_sw_user;
if (unlikely(check_for_xstate(buf_fx, buf_fx, &fx_sw_user))) {
/*
* Couldn't find the extended state information in the
* memory layout. Restore just the FP/SSE and init all
* the other extended state.
*/
state_size = sizeof(struct fxregs_state);
fx_only = 1;
} else {
state_size = fx_sw_user.xstate_size;
xfeatures = fx_sw_user.xfeatures;
}
}
if (ia32_fxstate) {
/*
* For 32-bit frames with fxstate, copy the user state to the
* thread's fpu state, reconstruct fxstate from the fsave
* header. Sanitize the copied state etc.
*/
struct fpu *fpu = &tsk->thread.fpu;
struct user_i387_ia32_struct env;
int err = 0;
/*
* Drop the current fpu which clears fpu->fpstate_active. This ensures
* that any context-switch during the copy of the new state,
* avoids the intermediate state from getting restored/saved.
* Thus avoiding the new restored state from getting corrupted.
* We will be ready to restore/save the state only after
* fpu->fpstate_active is again set.
*/
fpu__drop(fpu);
if (__copy_from_user(&fpu->state.xsave, buf_fx, state_size) ||
__copy_from_user(&env, buf, sizeof(env))) {
fpstate_init(&fpu->state);
err = -1;
} else {
sanitize_restored_xstate(tsk, &env, xfeatures, fx_only);
}
fpu->fpstate_active = 1;
if (use_eager_fpu()) {
preempt_disable();
fpu__restore(fpu);
preempt_enable();
}
return err;
} else {
/*
* For 64-bit frames and 32-bit fsave frames, restore the user
* state to the registers directly (with exceptions handled).
*/
user_fpu_begin();
if (copy_user_to_fpregs_zeroing(buf_fx, xfeatures, fx_only)) {
fpu__clear(fpu);
return -1;
}
}
return 0;
}
