void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
/* Initialize the console to provide early debug support */
(void)console_pl011_register(PLAT_SQ_BOOT_UART_BASE,
PLAT_SQ_BOOT_UART_CLK_IN_HZ,
SQ_CONSOLE_BAUDRATE, &console);
console_set_scope(&console.console, CONSOLE_FLAG_BOOT |
CONSOLE_FLAG_RUNTIME);
/* There are no parameters from BL2 if BL31 is a reset vector */
assert(arg0 == 0U);
assert(arg1 == 0U);
/* Initialize power controller before setting up topology */
plat_sq_pwrc_setup();
#ifdef SPD_opteed
struct draminfo di = {0};
sq_scp_get_draminfo(&di);
/*
* Check if OP-TEE has been loaded in Secure RAM allocated
* from DRAM1 region
*/
if ((di.base1 + di.size1) <= BL32_BASE) {
NOTICE("OP-TEE has been loaded by SCP firmware\n");
/* Populate entry point information for BL32 */
SET_PARAM_HEAD(&bl32_image_ep_info,
PARAM_EP,
VERSION_1,
0);
SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
bl32_image_ep_info.pc = BL32_BASE;
bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry();
} else {
NOTICE("OP-TEE has not been loaded by SCP firmware\n");
}
#endif /* SPD_opteed */
/* Populate entry point information for BL33 */
SET_PARAM_HEAD(&bl33_image_ep_info,
PARAM_EP,
VERSION_1,
0);
/*
* Tell BL31 where the non-trusted software image
* is located and the entry state information
*/
bl33_image_ep_info.pc = PRELOADED_BL33_BASE;
bl33_image_ep_info.spsr = sq_get_spsr_for_bl33_entry();
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
}
void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
u_register_t arg3, u_register_t arg4)
{
/* Initialize the console to provide early debug support */
console_pl011_register(CONSOLE_BASE, PL011_UART_CLK_IN_HZ,
PL011_BAUDRATE, &console);
/*
* Allow BL2 to see the whole Trusted RAM.
*/
bl2_el3_tzram_layout.total_base = BL2_RW_BASE;
bl2_el3_tzram_layout.total_size = BL31_LIMIT - BL2_RW_BASE;
}
/* Initialize the runtime console */
void arm_console_runtime_init(void)
{
#if MULTI_CONSOLE_API
int rc = console_pl011_register(PLAT_ARM_BL31_RUN_UART_BASE,
PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ,
ARM_CONSOLE_BAUDRATE,
&arm_runtime_console);
if (rc == 0)
panic();
console_set_scope(&arm_runtime_console.console, CONSOLE_FLAG_RUNTIME);
#else
(void)console_init(PLAT_ARM_BL31_RUN_UART_BASE,
PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ,
ARM_CONSOLE_BAUDRATE);
#endif /* MULTI_CONSOLE_API */
}
/*
* Perform any BL1 specific platform actions.
*/
void bl1_early_platform_setup(void)
{
unsigned int id, uart_base;
generic_delay_timer_init();
hikey960_read_boardid(&id);
if (id == 5300)
uart_base = PL011_UART5_BASE;
else
uart_base = PL011_UART6_BASE;
/* Initialize the console to provide early debug support */
console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ,
PL011_BAUDRATE, &console);
/* Allow BL1 to see the whole Trusted RAM */
bl1_tzram_layout.total_base = BL1_RW_BASE;
bl1_tzram_layout.total_size = BL1_RW_SIZE;
INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */
}
/* Initialize the console to provide early debug support */
void __init arm_console_boot_init(void)
{
#if MULTI_CONSOLE_API
int rc = console_pl011_register(PLAT_ARM_BOOT_UART_BASE,
PLAT_ARM_BOOT_UART_CLK_IN_HZ,
ARM_CONSOLE_BAUDRATE,
&arm_boot_console);
if (rc == 0) {
/*
* The crash console doesn't use the multi console API, it uses
* the core console functions directly. It is safe to call panic
* and let it print debug information.
*/
panic();
}
console_set_scope(&arm_boot_console.console, CONSOLE_FLAG_BOOT);
#else
(void)console_init(PLAT_ARM_BOOT_UART_BASE,
PLAT_ARM_BOOT_UART_CLK_IN_HZ,
ARM_CONSOLE_BAUDRATE);
#endif /* MULTI_CONSOLE_API */
}
