rtx
addr_for_mem_ref (struct mem_address *addr, addr_space_t as,
bool really_expand)
{
enum machine_mode address_mode = targetm.addr_space.address_mode (as);
enum machine_mode pointer_mode = targetm.addr_space.pointer_mode (as);
rtx address, sym, bse, idx, st, off;
struct mem_addr_template *templ;
if (addr->step && !integer_onep (addr->step))
st = immed_double_int_const (tree_to_double_int (addr->step), pointer_mode);
else
st = NULL_RTX;
if (addr->offset && !integer_zerop (addr->offset))
off = immed_double_int_const
(double_int_sext (tree_to_double_int (addr->offset),
TYPE_PRECISION (TREE_TYPE (addr->offset))),
pointer_mode);
else
off = NULL_RTX;
if (!really_expand)
{
unsigned int templ_index
= TEMPL_IDX (as, addr->symbol, addr->base, addr->index, st, off);
if (templ_index
>= VEC_length (mem_addr_template, mem_addr_template_list))
VEC_safe_grow_cleared (mem_addr_template, gc, mem_addr_template_list,
templ_index + 1);
/* Reuse the templates for addresses, so that we do not waste memory. */
templ = VEC_index (mem_addr_template, mem_addr_template_list, templ_index);
if (!templ->ref)
{
sym = (addr->symbol ?
gen_rtx_SYMBOL_REF (pointer_mode, ggc_strdup ("test_symbol"))
: NULL_RTX);
bse = (addr->base ?
gen_raw_REG (pointer_mode, LAST_VIRTUAL_REGISTER + 1)
: NULL_RTX);
idx = (addr->index ?
gen_raw_REG (pointer_mode, LAST_VIRTUAL_REGISTER + 2)
: NULL_RTX);
gen_addr_rtx (pointer_mode, sym, bse, idx,
st? const0_rtx : NULL_RTX,
off? const0_rtx : NULL_RTX,
&templ->ref,
&templ->step_p,
&templ->off_p);
}
if (st)
*templ->step_p = st;
if (off)
*templ->off_p = off;
return templ->ref;
}
/* Otherwise really expand the expressions. */
sym = (addr->symbol
? expand_expr (addr->symbol, NULL_RTX, pointer_mode, EXPAND_NORMAL)
: NULL_RTX);
bse = (addr->base
? expand_expr (addr->base, NULL_RTX, pointer_mode, EXPAND_NORMAL)
: NULL_RTX);
idx = (addr->index
? expand_expr (addr->index, NULL_RTX, pointer_mode, EXPAND_NORMAL)
: NULL_RTX);
gen_addr_rtx (pointer_mode, sym, bse, idx, st, off, &address, NULL, NULL);
if (pointer_mode != address_mode)
address = convert_memory_address (address_mode, address);
return address;
}
static rtx
aarch64_simd_expand_args (rtx target, int icode, int have_retval,
tree exp, builtin_simd_arg *args)
{
rtx pat;
rtx op[SIMD_MAX_BUILTIN_ARGS + 1]; /* First element for result operand. */
int opc = 0;
if (have_retval)
{
machine_mode tmode = insn_data[icode].operand[0].mode;
if (!target
|| GET_MODE (target) != tmode
|| !(*insn_data[icode].operand[0].predicate) (target, tmode))
target = gen_reg_rtx (tmode);
op[opc++] = target;
}
for (;;)
{
builtin_simd_arg thisarg = args[opc - have_retval];
if (thisarg == SIMD_ARG_STOP)
break;
else
{
tree arg = CALL_EXPR_ARG (exp, opc - have_retval);
enum machine_mode mode = insn_data[icode].operand[opc].mode;
op[opc] = expand_normal (arg);
switch (thisarg)
{
case SIMD_ARG_COPY_TO_REG:
if (POINTER_TYPE_P (TREE_TYPE (arg)))
op[opc] = convert_memory_address (Pmode, op[opc]);
/*gcc_assert (GET_MODE (op[opc]) == mode); */
if (!(*insn_data[icode].operand[opc].predicate)
(op[opc], mode))
op[opc] = copy_to_mode_reg (mode, op[opc]);
break;
case SIMD_ARG_LANE_INDEX:
/* Must be a previous operand into which this is an index. */
gcc_assert (opc > 0);
if (CONST_INT_P (op[opc]))
{
machine_mode vmode = insn_data[icode].operand[opc - 1].mode;
aarch64_simd_lane_bounds (op[opc],
0, GET_MODE_NUNITS (vmode), exp);
/* Keep to GCC-vector-extension lane indices in the RTL. */
op[opc] = GEN_INT (ENDIAN_LANE_N (vmode, INTVAL (op[opc])));
}
/* Fall through - if the lane index isn't a constant then
the next case will error. */
case SIMD_ARG_CONSTANT:
if (!(*insn_data[icode].operand[opc].predicate)
(op[opc], mode))
{
error ("%Kargument %d must be a constant immediate",
exp, opc + 1 - have_retval);
return const0_rtx;
}
break;
case SIMD_ARG_STOP:
gcc_unreachable ();
}
opc++;
}
}
switch (opc)
{
case 1:
pat = GEN_FCN (icode) (op[0]);
break;
case 2:
pat = GEN_FCN (icode) (op[0], op[1]);
break;
case 3:
pat = GEN_FCN (icode) (op[0], op[1], op[2]);
break;
case 4:
pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
break;
case 5:
pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]);
break;
case 6:
pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5]);
break;
default:
gcc_unreachable ();
}
if (!pat)
return NULL_RTX;
emit_insn (pat);
return target;
}
static rtx
aarch64_simd_expand_args (rtx target, int icode, int have_retval,
tree exp, builtin_simd_arg *args)
{
rtx pat;
tree arg[SIMD_MAX_BUILTIN_ARGS];
rtx op[SIMD_MAX_BUILTIN_ARGS];
machine_mode tmode = insn_data[icode].operand[0].mode;
machine_mode mode[SIMD_MAX_BUILTIN_ARGS];
int argc = 0;
if (have_retval
&& (!target
|| GET_MODE (target) != tmode
|| !(*insn_data[icode].operand[0].predicate) (target, tmode)))
target = gen_reg_rtx (tmode);
for (;;)
{
builtin_simd_arg thisarg = args[argc];
if (thisarg == SIMD_ARG_STOP)
break;
else
{
arg[argc] = CALL_EXPR_ARG (exp, argc);
op[argc] = expand_normal (arg[argc]);
mode[argc] = insn_data[icode].operand[argc + have_retval].mode;
switch (thisarg)
{
case SIMD_ARG_COPY_TO_REG:
if (POINTER_TYPE_P (TREE_TYPE (arg[argc])))
op[argc] = convert_memory_address (Pmode, op[argc]);
/*gcc_assert (GET_MODE (op[argc]) == mode[argc]); */
if (!(*insn_data[icode].operand[argc + have_retval].predicate)
(op[argc], mode[argc]))
op[argc] = copy_to_mode_reg (mode[argc], op[argc]);
break;
case SIMD_ARG_LANE_INDEX:
/* Must be a previous operand into which this is an index. */
gcc_assert (argc > 0);
if (CONST_INT_P (op[argc]))
{
enum machine_mode vmode = mode[argc - 1];
aarch64_simd_lane_bounds (op[argc],
0, GET_MODE_NUNITS (vmode));
/* Keep to GCC-vector-extension lane indices in the RTL. */
op[argc] = GEN_INT (ENDIAN_LANE_N (vmode, INTVAL (op[argc])));
}
/* Fall through - if the lane index isn't a constant then
the next case will error. */
case SIMD_ARG_CONSTANT:
if (!(*insn_data[icode].operand[argc + have_retval].predicate)
(op[argc], mode[argc]))
{
error_at (EXPR_LOCATION (exp), "incompatible type for argument %d, "
"expected %<const int%>", argc + 1);
return const0_rtx;
}
break;
case SIMD_ARG_STOP:
gcc_unreachable ();
}
argc++;
}
}
if (have_retval)
switch (argc)
{
case 1:
pat = GEN_FCN (icode) (target, op[0]);
break;
case 2:
pat = GEN_FCN (icode) (target, op[0], op[1]);
break;
case 3:
pat = GEN_FCN (icode) (target, op[0], op[1], op[2]);
break;
case 4:
pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3]);
break;
case 5:
pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4]);
break;
default:
gcc_unreachable ();
}
else
switch (argc)
{
case 1:
pat = GEN_FCN (icode) (op[0]);
break;
case 2:
pat = GEN_FCN (icode) (op[0], op[1]);
break;
case 3:
pat = GEN_FCN (icode) (op[0], op[1], op[2]);
break;
case 4:
pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
break;
case 5:
pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]);
break;
default:
gcc_unreachable ();
}
if (!pat)
return NULL_RTX;
emit_insn (pat);
return target;
}
static rtx
aarch64_simd_expand_args (rtx target, int icode, int have_retval,
tree exp, builtin_simd_arg *args)
{
rtx pat;
tree arg[SIMD_MAX_BUILTIN_ARGS];
rtx op[SIMD_MAX_BUILTIN_ARGS];
machine_mode tmode = insn_data[icode].operand[0].mode;
machine_mode mode[SIMD_MAX_BUILTIN_ARGS];
int argc = 0;
if (have_retval
&& (!target
|| GET_MODE (target) != tmode
|| !(*insn_data[icode].operand[0].predicate) (target, tmode)))
target = gen_reg_rtx (tmode);
for (;;)
{
builtin_simd_arg thisarg = args[argc];
if (thisarg == SIMD_ARG_STOP)
break;
else
{
arg[argc] = CALL_EXPR_ARG (exp, argc);
op[argc] = expand_normal (arg[argc]);
mode[argc] = insn_data[icode].operand[argc + have_retval].mode;
switch (thisarg)
{
case SIMD_ARG_COPY_TO_REG:
if (POINTER_TYPE_P (TREE_TYPE (arg[argc])))
op[argc] = convert_memory_address (Pmode, op[argc]);
/*gcc_assert (GET_MODE (op[argc]) == mode[argc]); */
if (!(*insn_data[icode].operand[argc + have_retval].predicate)
(op[argc], mode[argc]))
op[argc] = copy_to_mode_reg (mode[argc], op[argc]);
break;
case SIMD_ARG_CONSTANT:
if (!(*insn_data[icode].operand[argc + have_retval].predicate)
(op[argc], mode[argc]))
{
error_at (EXPR_LOCATION (exp), "incompatible type for argument %d, "
"expected %<const int%>", argc + 1);
return const0_rtx;
}
break;
case SIMD_ARG_STOP:
gcc_unreachable ();
}
argc++;
}
}
if (have_retval)
switch (argc)
{
case 1:
pat = GEN_FCN (icode) (target, op[0]);
break;
case 2:
pat = GEN_FCN (icode) (target, op[0], op[1]);
break;
case 3:
pat = GEN_FCN (icode) (target, op[0], op[1], op[2]);
break;
case 4:
pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3]);
break;
case 5:
pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4]);
break;
default:
gcc_unreachable ();
}
else
switch (argc)
{
case 1:
pat = GEN_FCN (icode) (op[0]);
break;
case 2:
pat = GEN_FCN (icode) (op[0], op[1]);
break;
case 3:
pat = GEN_FCN (icode) (op[0], op[1], op[2]);
break;
case 4:
pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]);
break;
case 5:
pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]);
break;
default:
gcc_unreachable ();
}
if (!pat)
return NULL_RTX;
emit_insn (pat);
return target;
}
