static int nrf51_flash_write(struct target_flash *f,
uint32_t dest, const void *src, size_t len)
{
target *t = f->t;
uint32_t data[2 + len/4];
/* FIXME rewrite stub to use register args */
/* Construct data buffer used by stub */
data[0] = dest;
data[1] = len; /* length must always be a multiple of 4 */
memcpy((uint8_t *)&data[2], src, len);
/* Enable write */
target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_WEN);
/* Poll for NVMC_READY */
while (target_mem_read32(t, NRF51_NVMC_READY) == 0)
if(target_check_error(t))
return -1;
/* Write stub and data to target ram and call stub */
target_mem_write(t, SRAM_BASE, nrf51_flash_write_stub,
sizeof(nrf51_flash_write_stub));
target_mem_write(t, STUB_BUFFER_BASE, data, len + 8);
cortexm_run_stub(t, SRAM_BASE, 0, 0, 0, 0);
/* Return to read-only */
target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_REN);
return 0;
}
int lmi_flash_write(struct target_flash *f,
uint32_t dest, const void *src, size_t len)
{
target *t = f->t;
target_mem_write(t, SRAM_BASE, lmi_flash_write_stub,
sizeof(lmi_flash_write_stub));
target_mem_write(t, STUB_BUFFER_BASE, src, len);
return cortexm_run_stub(t, SRAM_BASE, dest, STUB_BUFFER_BASE, len, 0);
}
static int stm32f4_flash_write(struct target_flash *f,
uint32_t dest, const void *src, size_t len)
{
/* Write buffer to target ram call stub */
target_mem_write(f->t, SRAM_BASE, stm32f4_flash_write_stub,
sizeof(stm32f4_flash_write_stub));
target_mem_write(f->t, STUB_BUFFER_BASE, src, len);
return cortexm_run_stub(f->t, SRAM_BASE, dest,
STUB_BUFFER_BASE, len, 0);
}
static int stm32f1_flash_write(struct target_flash *f,
target_addr dest, const void *src, size_t len)
{
target *t = f->t;
/* Write stub and data to target ram and set PC */
target_mem_write(t, SRAM_BASE, stm32f1_flash_write_stub,
sizeof(stm32f1_flash_write_stub));
target_mem_write(t, STUB_BUFFER_BASE, src, len);
return cortexm_run_stub(t, SRAM_BASE, dest, STUB_BUFFER_BASE, len, 0);
}
/**
* Write flash page by page
*/
static int efm32_flash_write(struct target_flash *f,
target_addr dest, const void *src, size_t len)
{
(void)len;
target *t = f->t;
/* Write flashloader */
target_mem_write(t, SRAM_BASE, efm32_flash_write_stub,
sizeof(efm32_flash_write_stub));
/* Write Buffer */
target_mem_write(t, STUB_BUFFER_BASE, src, len);
/* Run flashloader */
return cortexm_run_stub(t, SRAM_BASE, dest, STUB_BUFFER_BASE, len, 0);
return 0;
}
static int stm32f4_flash_write(struct target_flash *f,
target_addr dest, const void *src, size_t len)
{
/* Translate ITCM addresses to AXIM */
if ((dest >= ITCM_BASE) && (dest < AXIM_BASE)) {
dest = AXIM_BASE + (dest - ITCM_BASE);
}
/* Write buffer to target ram call stub */
if (((struct stm32f4_flash *)f)->psize == 32)
target_mem_write(f->t, SRAM_BASE, stm32f4_flash_write_x32_stub,
sizeof(stm32f4_flash_write_x32_stub));
else
target_mem_write(f->t, SRAM_BASE, stm32f4_flash_write_x8_stub,
sizeof(stm32f4_flash_write_x8_stub));
target_mem_write(f->t, STUB_BUFFER_BASE, src, len);
return cortexm_run_stub(f->t, SRAM_BASE, dest,
STUB_BUFFER_BASE, len, 0);
}
static int nrf51_flash_write(struct target_flash *f,
target_addr dest, const void *src, size_t len)
{
target *t = f->t;
/* Enable write */
target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_WEN);
/* Poll for NVMC_READY */
while (target_mem_read32(t, NRF51_NVMC_READY) == 0)
if(target_check_error(t))
return -1;
/* Write stub and data to target ram and call stub */
target_mem_write(t, SRAM_BASE, nrf51_flash_write_stub,
sizeof(nrf51_flash_write_stub));
target_mem_write(t, STUB_BUFFER_BASE, src, len);
int ret = cortexm_run_stub(t, SRAM_BASE, dest,
STUB_BUFFER_BASE, len, 0);
/* Return to read-only */
target_mem_write32(t, NRF51_NVMC_CONFIG, NRF51_NVMC_CONFIG_REN);
return ret;
}
