void jz_otg_sft_id(int level) { if (level) { cpm_set_bit(USBRDT_IDDIG_REG, CPM_USBRDT); printk("sft id ==================== 1\n"); } else { cpm_clear_bit(USBRDT_IDDIG_REG, CPM_USBRDT); printk("sft id ==================== 0\n"); } cpm_set_bit(USBRDT_IDDIG_EN, CPM_USBRDT); if (!jz_otg_phy_is_suspend()) mdelay(150); else sft_id_set = true; }
//static int ahbm_read_proc(char *page, char **start, off_t off, // int count, int *eof, void *data) static int ahbm_show(struct seq_file *m, void *v) { int i = 0, len = 0; int ignore_time = (sum/period)-rate; struct saved_value *vbuf; vbuf = vmalloc(sizeof(struct saved_value) * period); if(!vbuf) { seq_printf(m,"//period = %d\nsum = %dms\nrate = %dms",period,sum,rate); seq_printf(m,"malloc err.\n"); return len; } //cpm_clear_bit(11,CPM_CLKGR); cpm_clear_bit(4,CPM_CLKGR); while(i<period) { outl(0x0,DDR_MC); outl(0x0,DDR_RESULT_1); outl(0x0,DDR_RESULT_2); outl(0x0,DDR_RESULT_3); outl(0x0,DDR_RESULT_4); outl(0x1,DDR_MC); ahbm_restart(CIM); ahbm_restart(AHB0); ahbm_restart(GPU); ahbm_restart(LCD); ahbm_restart(XXX); ahbm_restart(AHB2); msleep(rate); outl(0x0,DDR_MC); ahbm_stop(CIM); ahbm_stop(AHB0); ahbm_stop(GPU); ahbm_stop(LCD); ahbm_stop(XXX); ahbm_stop(AHB2); save_value(&vbuf[i]); msleep(ignore_time); i++; } cpm_set_bit(4,CPM_CLKGR); seq_printf(m,"//period=%d sum=%dms rate = %dms\n",period,sum,rate); i=0; while(i<period) { print_value(m,&vbuf[i]); seq_printf(m,"SAMPLE_FINISH:%d\n",i); i++; } vfree(vbuf); return 0; }
static int cpm_gate_enable(struct clk *clk,int on){ int bit = CLK_GATE_BIT(clk->flags); unsigned int clkgr[2] = {CPM_CLKGR}; unsigned long flags; spin_lock_irqsave(&cpm_gate_lock,flags); if(on) { cpm_clear_bit(bit % 32, clkgr[bit / 32]); } else { cpm_set_bit(bit % 32, clkgr[bit / 32]); } spin_unlock_irqrestore(&cpm_gate_lock,flags); return 0; }
void jz_otg_phy_suspend(int suspend) { if (!suspend && jz_otg_phy_is_suspend()) { printk("EN PHY\n"); cpm_set_bit(7, CPM_OPCR); if (sft_id_set == true) mdelay(150); /*2d6c0 phy clocks*/ sft_id_set = false; udelay(45); } else if (suspend && !jz_otg_phy_is_suspend()) { printk("DIS PHY\n"); cpm_clear_bit(7, CPM_OPCR); udelay(5); } }
static void cpm_pwc_poweroff(unsigned long data) { int t; unsigned long flags; struct cpm_pwc *pwc = (struct cpm_pwc *)data; if(strcmp(pwc->name, "pwc_lcd") == 0) return; spin_lock_irqsave(&cpm_pwc_ctrl.spin_lock,flags); t = cpm_test_bit(pwc->ctrl_bit,pwc->reg_offset); //t == 0 is power on if(!t) { cpm_set_bit(pwc->ctrl_bit,pwc->reg_offset); while(!cpm_test_bit(pwc->wait_bit,pwc->reg_offset)); } spin_unlock_irqrestore(&cpm_pwc_ctrl.spin_lock,flags); }
void jzsoc_cpu_die(unsigned int cpu) { unsigned long flags; unsigned int status; if (cpu == 0) /* FIXME */ return; local_irq_save(flags); cpumask_clear_cpu(cpu, cpu_ready); cpumask_clear_cpu(cpu, &cpu_start); cpumask_clear_cpu(cpu, &cpu_running); wmb(); do{ status = get_smp_status(); }while(!(status & (1<<(cpu+16)))); cpm_pwc_disable(scpu_pwc); cpm_set_bit(15,CPM_CLKGR1); local_irq_restore(flags); printk("disable cpu %d\n",cpu); }
static int vpu_reset(struct jz_vpu *vpu) { int timeout = 0xffffff; unsigned int srbc = cpm_inl(CPM_SRBC); cpm_set_bit(30, CPM_SRBC); while (!(cpm_inl(CPM_SRBC) & (1 << 29)) && --timeout); if (timeout == 0) { dev_warn(vpu->dev, "[%d:%d] wait stop ack timeout\n", current->tgid, current->pid); cpm_outl(srbc, CPM_SRBC); return -1; } else { cpm_outl(srbc | (1 << 31), CPM_SRBC); cpm_outl(srbc, CPM_SRBC); } return 0; }
void __init cpm_reset(void) { #ifndef CONFIG_FPGA_TEST unsigned int cpm_clkgr; cpm_clkgr = cpm_inl(CPM_CLKGR); cpm_clkgr |= 0x5ed83fff; cpm_clkgr &= (~(1 << 21)); /* keep dsi and lcd clock on */ cpm_clkgr &= (~(1 << 24)); cpm_clkgr &= (~(1 << 26)); cpm_outl(cpm_clkgr, CPM_CLKGR); cpm_outl(0x29ff, CPM_CLKGR1); cpm_outl(0x08000000, CPM_USBCDR); /* warn:when switch cpu freq ,the 23(sclka mux) bit should be set */ cpm_set_bit(23,CPM_CPCCR); mdelay(1); #endif }
void jz_otg_phy_init(otg_mode_t mode) { unsigned int usbpcr1; /* select dwc otg */ cpm_set_bit(8, CPM_USBPCR1); cpm_set_bit(9, CPM_USBPCR1); cpm_set_bit(28, CPM_USBPCR1); cpm_set_bit(29, CPM_USBPCR1); cpm_set_bit(30, CPM_USBPCR1); /* select utmi data bus width of port0 to 16bit/30M */ cpm_clear_bit(USBPCR1_WORD_IF0, CPM_USBPCR1); /* select utmi data bus width of port0 to 8bit/60M */ /*cpm_set_bit(USBPCR1_WORD_IF0, CPM_USBPCR1);*/ usbpcr1 = cpm_inl(CPM_USBPCR1); usbpcr1 &= ~(0x7 << 23); usbpcr1 |= (5 << 23); cpm_outl(usbpcr1, CPM_USBPCR1); /* fil */ cpm_outl(0, CPM_USBVBFIL); /* rdt */ cpm_outl(0x96, CPM_USBRDT); /* rdt - filload_en */ cpm_set_bit(USBRDT_VBFIL_LD_EN, CPM_USBRDT); /* TXRISETUNE & TXVREFTUNE. */ //cpm_outl(0x3f, CPM_USBPCR); //cpm_outl(0x35, CPM_USBPCR); /* enable tx pre-emphasis */ //cpm_set_bit(USBPCR_TXPREEMPHTUNE, CPM_USBPCR); /* OTGTUNE adjust */ //cpm_outl(7 << 14, CPM_USBPCR); cpm_outl(0x8380385a, CPM_USBPCR); if (mode == DEVICE_ONLY) { printk("DWC IN DEVICE ONLY MODE\n"); cpm_clear_bit(USBPCR_USB_MODE, CPM_USBPCR); cpm_clear_bit(USBPCR_OTG_DISABLE, CPM_USBPCR); cpm_clear_bit(USBPCR_SIDDQ, CPM_USBPCR); } else { unsigned int tmp; printk("DWC IN OTG MODE\n"); tmp = cpm_inl(CPM_USBPCR); tmp |= 1 << USBPCR_USB_MODE | 1 << USBPCR_COMMONONN; tmp &= ~(1 << USBPCR_OTG_DISABLE | 1 << USBPCR_SIDDQ | 0x03 << USBPCR_IDPULLUP_MASK | 1 << USBPCR_VBUSVLDEXT | 1 << USBPCR_VBUSVLDEXTSEL); cpm_outl(tmp, CPM_USBPCR); } /*cpm_set_bit(USBRDT_UTMI_RST, CPM_USBRDT);*/ /*udelay(10);*/ cpm_set_bit(USBPCR_POR, CPM_USBPCR); cpm_clear_bit(USBRDT_UTMI_RST, CPM_USBRDT); cpm_set_bit(SRBC_USB_SR, CPM_SRBC); udelay(5); cpm_clear_bit(USBPCR_POR, CPM_USBPCR); udelay(10); cpm_set_bit(OPCR_SPENDN0, CPM_OPCR); udelay(550); cpm_set_bit(USBRDT_UTMI_RST, CPM_USBRDT); udelay(10); cpm_clear_bit(SRBC_USB_SR, CPM_SRBC); }
void jz_otg_ctr_reset(void) { cpm_set_bit(SRBC_USB_SR, CPM_SRBC); udelay(10); cpm_clear_bit(SRBC_USB_SR, CPM_SRBC); }
void jz_otg_phy_powerdown(void) { cpm_set_bit(USBPCR_OTG_DISABLE,CPM_USBPCR); cpm_set_bit(USBPCR_SIDDQ ,CPM_USBPCR); }
int cpm_start_ohci(void) { int tmp; static int has_reset = 0; /* The PLL uses CLKCORE as reference */ tmp = cpm_inl(CPM_USBPCR1); tmp |= (0x3<<26); cpm_outl(tmp,CPM_USBPCR1); /* selects the reference clock frequency 48M */ tmp = cpm_inl(CPM_USBPCR1); tmp &= ~(0x3<<24); switch(JZ_EXTAL) { case 24000000: tmp |= (1<<24);break; case 48000000: tmp |= (2<<24);break; case 19200000: tmp |= (3<<24);break; case 12000000: default: tmp |= (0<<24);break; } cpm_outl(tmp,CPM_USBPCR1); /* Configurate UHC IBSOP */ tmp = cpm_inl(CPM_USBPCR1); tmp &= ~(7 << 14); tmp |= (1 << 14); cpm_outl(tmp,CPM_USBPCR1); /* Configurate UHC XP */ tmp = cpm_inl(CPM_USBPCR1); tmp &= ~(3 << 12); cpm_outl(tmp,CPM_USBPCR1); /* Configurate UHC SP */ tmp = cpm_inl(CPM_USBPCR1); tmp &= ~(7 << 9); tmp |= (1 << 9); cpm_outl(tmp,CPM_USBPCR1); /* Configurate UHC SM */ tmp = cpm_inl(CPM_USBPCR1); tmp &= ~(7 << 6); tmp |= (1 << 6); cpm_outl(tmp,CPM_USBPCR1); /* Disable overcurrent */ cpm_clear_bit(4,CPM_USBPCR1); /* Enable OHCI clock */ cpm_set_bit(5,CPM_USBPCR1); cpm_set_bit(17,CPM_USBPCR1); cpm_set_bit(6, CPM_OPCR); /* OTG PHY reset */ cpm_set_bit(22, CPM_USBPCR); udelay(30); cpm_clear_bit(22, CPM_USBPCR); udelay(300); /* UHC soft reset */ if(!has_reset) { cpm_set_bit(14, CPM_SRBC); udelay(300); cpm_clear_bit(14, CPM_SRBC); udelay(300); has_reset = 1; } printk(KERN_DEBUG __FILE__ ": Clock to USB host has been enabled \n"); return 0; }
void jz_otg_phy_init(otg_mode_t mode) { unsigned int ref_clk_div = CONFIG_EXTAL_CLOCK / 24; unsigned int usbpcr1, usbrdt; /* select dwc otg */ cpm_set_bit(USBPCR1_USB_SEL, CPM_USBPCR1); /* select utmi data bus width of port0 to 16bit/30M */ cpm_set_bit(USBPCR1_WORD_IF0, CPM_USBPCR1); usbpcr1 = cpm_inl(CPM_USBPCR1); usbpcr1 &= ~(0x3 << 24 | 1 << 30); usbpcr1 |= (ref_clk_div << 24); cpm_outl(usbpcr1, CPM_USBPCR1); /*unsuspend*/ cpm_set_bit(7, CPM_OPCR); udelay(45); cpm_clear_bit(USBPCR_SIDDQ, CPM_USBPCR); /* fil */ cpm_outl(0, CPM_USBVBFIL); /* rdt */ usbrdt = cpm_inl(CPM_USBRDT); usbrdt &= ~(USBRDT_VBFIL_LD_EN | ((1 << 23) - 1)); usbrdt |= 0x96; cpm_outl(usbrdt, CPM_USBRDT); /* rdt - filload_en */ cpm_set_bit(USBRDT_VBFIL_LD_EN, CPM_USBRDT); /* TXRISETUNE & TXVREFTUNE. */ //cpm_outl(0x3f, CPM_USBPCR); //cpm_outl(0x35, CPM_USBPCR); /* enable tx pre-emphasis */ //cpm_set_bit(USBPCR_TXPREEMPHTUNE, CPM_USBPCR); /* OTGTUNE adjust */ //cpm_outl(7 << 14, CPM_USBPCR); cpm_outl(0x83803857, CPM_USBPCR); if (mode == DEVICE_ONLY) { pr_info("DWC IN DEVICE ONLY MODE\n"); cpm_clear_bit(USBPCR_USB_MODE, CPM_USBPCR); cpm_clear_bit(USBPCR_OTG_DISABLE, CPM_USBPCR); cpm_clear_bit(USBPCR_SIDDQ, CPM_USBPCR); cpm_set_bit(USBPCR_COMMONONN, CPM_USBPCR); } else { unsigned int tmp; pr_info("DWC IN OTG MODE\n"); tmp = cpm_inl(CPM_USBPCR); tmp |= 1 << USBPCR_USB_MODE | 1 << USBPCR_COMMONONN; tmp &= ~(1 << USBPCR_OTG_DISABLE | 1 << USBPCR_SIDDQ | 0x03 << USBPCR_IDPULLUP_MASK | 1 << USBPCR_VBUSVLDEXT | 1 << USBPCR_VBUSVLDEXTSEL); cpm_outl(tmp, CPM_USBPCR); } cpm_set_bit(USBPCR_POR, CPM_USBPCR); mdelay(1); cpm_clear_bit(USBPCR_POR, CPM_USBPCR); mdelay(1); }