int board_eth_init(bd_t *bis) { int ret; uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; uint32_t ctrl_val; /* try reading mac address from efuse */ mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); mac_addr[0] = (mac_hi & 0xFF0000) >> 16; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = mac_hi & 0xFF; mac_addr[3] = (mac_lo & 0xFF0000) >> 16; mac_addr[4] = (mac_lo & 0xFF00) >> 8; mac_addr[5] = mac_lo & 0xFF; if (!env_get("ethaddr")) { printf("<ethaddr> not set. Validating first E-fuse MAC\n"); if (is_valid_ethaddr(mac_addr)) eth_env_set_enetaddr("ethaddr", mac_addr); } mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); mac_addr[0] = (mac_hi & 0xFF0000) >> 16; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = mac_hi & 0xFF; mac_addr[3] = (mac_lo & 0xFF0000) >> 16; mac_addr[4] = (mac_lo & 0xFF00) >> 8; mac_addr[5] = mac_lo & 0xFF; if (!env_get("eth1addr")) { if (is_valid_ethaddr(mac_addr)) eth_env_set_enetaddr("eth1addr", mac_addr); } ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); ctrl_val |= 0x22; writel(ctrl_val, (*ctrl)->control_core_control_io1); if (*omap_si_rev == DRA722_ES1_0) cpsw_data.active_slave = 1; if (board_is_dra72x_revc_or_later()) { cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII_ID; cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII_ID; } ret = cpsw_register(&cpsw_data); if (ret < 0) printf("Error %d registering CPSW switch\n", ret); return ret; }
int board_eth_init(bd_t *bis) { int ret; uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; uint32_t ctrl_val; /* try reading mac address from efuse */ mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); mac_addr[0] = (mac_hi & 0xFF0000) >> 16; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = mac_hi & 0xFF; mac_addr[3] = (mac_lo & 0xFF0000) >> 16; mac_addr[4] = (mac_lo & 0xFF00) >> 8; mac_addr[5] = mac_lo & 0xFF; if (!getenv("ethaddr")) { printf("<ethaddr> not set. Validating first E-fuse MAC\n"); if (is_valid_ethaddr(mac_addr)) eth_setenv_enetaddr("ethaddr", mac_addr); } mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); mac_addr[0] = (mac_hi & 0xFF0000) >> 16; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = mac_hi & 0xFF; mac_addr[3] = (mac_lo & 0xFF0000) >> 16; mac_addr[4] = (mac_lo & 0xFF00) >> 8; mac_addr[5] = mac_lo & 0xFF; if (!getenv("eth1addr")) { if (is_valid_ethaddr(mac_addr)) eth_setenv_enetaddr("eth1addr", mac_addr); } ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); ctrl_val |= 0x22; writel(ctrl_val, (*ctrl)->control_core_control_io1); /* The phy address for the AM57xx IDK are different than x15 */ if (board_is_am572x_idk() || board_is_am571x_idk()) { cpsw_data.slave_data[0].phy_addr = 0; cpsw_data.slave_data[1].phy_addr = 1; } ret = cpsw_register(&cpsw_data); if (ret < 0) printf("Error %d registering CPSW switch\n", ret); return ret; }
int board_eth_init(bd_t *bis) { int rv, n = 0; writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; rv = cpsw_register(&cpsw_data); if (rv < 0) printf("Error %d registering CPSW switch\n", rv); else n += rv; return n; }
int board_eth_init(bd_t *bis) { int rv = 0; char mac_addr[6]; const char *mac = 0; uint32_t mac_hi, mac_lo; /* try reading mac address from efuse */ mac_lo = readl(&cdev->macid0l); mac_hi = readl(&cdev->macid0h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) if (!getenv("ethaddr")) { #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USE_FDT) printf("<ethaddr> not set. trying DTB ... "); mac = dtbmacaddr(0); #endif if (!mac) { printf("<ethaddr> not set. validating E-fuse MAC ... "); if (is_valid_ether_addr((const u8 *)mac_addr)) mac = (const char *)mac_addr; } if (mac) { printf("using: %pM on ", mac); eth_setenv_enetaddr("ethaddr", (const u8 *)mac); } } writel(MII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII; cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; rv = cpsw_register(&cpsw_data); if (rv < 0) { printf("Error %d registering CPSW switch\n", rv); return 0; } #endif /* CONFIG_DRIVER_TI_CPSW, ... */ return rv; }
int board_eth_init(bd_t *bis) { struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; int n = 0; int rv; factoryset_setenv(); /* Set rgmii mode and enable rmii clock to be sourced from chip */ writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel); rv = cpsw_register(&cpsw_data); if (rv < 0) printf("Error %d registering CPSW switch\n", rv); else n += rv; return n; }
mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("ethaddr", mac_addr); else goto try_usbether; } writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel); rv = cpsw_register(&cpsw_data); if (rv < 0) printf("Error %d registering CPSW switch\n", rv); else n += rv; try_usbether: #endif #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD) rv = usb_eth_initialize(bis); if (rv < 0) printf("Error %d registering USB_ETHER\n", rv); else n += rv; #endif return n;
int board_eth_init(bd_t *bis) { int rv; uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; /* try reading mac address from efuse */ mac_lo = readl(&cdev->macid0l); mac_hi = readl(&cdev->macid0h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; if (!env_get("ethaddr")) { puts("<ethaddr> not set. Validating first E-fuse MAC\n"); if (is_valid_ethaddr(mac_addr)) eth_env_set_enetaddr("ethaddr", mac_addr); } mac_lo = readl(&cdev->macid1l); mac_hi = readl(&cdev->macid1h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; if (!env_get("eth1addr")) { if (is_valid_ethaddr(mac_addr)) eth_env_set_enetaddr("eth1addr", mac_addr); } if (board_is_eposevm()) { writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII; cpsw_slaves[0].phy_addr = 16; } else if (board_is_sk()) { writel(RGMII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; cpsw_slaves[0].phy_addr = 4; cpsw_slaves[1].phy_addr = 5; } else if (board_is_idk()) { writel(RGMII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; cpsw_slaves[0].phy_addr = 0; } else { writel(RGMII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RGMII; cpsw_slaves[0].phy_addr = 0; } rv = cpsw_register(&cpsw_data); if (rv < 0) printf("Error %d registering CPSW switch\n", rv); return rv; }
int board_eth_init(bd_t *bis) { int rv, n = 0; uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; __maybe_unused struct am335x_baseboard_id header; /* try reading mac address from efuse */ mac_lo = readl(&cdev->macid0l); mac_hi = readl(&cdev->macid0h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) if (!getenv("ethaddr")) { printf("<ethaddr> not set. Validating first E-fuse MAC\n"); if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("ethaddr", mac_addr); } #ifdef CONFIG_DRIVER_TI_CPSW mac_lo = readl(&cdev->macid1l); mac_hi = readl(&cdev->macid1h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; if (!getenv("eth1addr")) { if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("eth1addr", mac_addr); } if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); if (board_is_bone(&header) || board_is_bone_lt(&header) || board_is_idk(&header)) { writel(MII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; } else { writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; } rv = cpsw_register(&cpsw_data); if (rv < 0) printf("Error %d registering CPSW switch\n", rv); else n += rv; #endif /* * * CPSW RGMII Internal Delay Mode is not supported in all PVT * operating points. So we must set the TX clock delay feature * in the AR8051 PHY. Since we only support a single ethernet * device in U-Boot, we only do this for the first instance. */ #define AR8051_PHY_DEBUG_ADDR_REG 0x1d #define AR8051_PHY_DEBUG_DATA_REG 0x1e #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 #define AR8051_RGMII_TX_CLK_DLY 0x100 if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) { const char *devname; devname = miiphy_get_current_dev(); miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, AR8051_DEBUG_RGMII_CLK_DLY_REG); miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, AR8051_RGMII_TX_CLK_DLY); } #endif #if defined(CONFIG_USB_ETHER) && \ (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("usbnet_devaddr", mac_addr); rv = usb_eth_initialize(bis); if (rv < 0) printf("Error %d registering USB_ETHER\n", rv); else n += rv; #endif return n; }
int board_eth_init(bd_t *bis) { int rv, ret = 0; uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; /* try reading mac address from efuse */ mac_lo = readl(&cdev->macid0l); mac_hi = readl(&cdev->macid0h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) if (!getenv("ethaddr")) { debug("<ethaddr> not set. Reading from E-fuse\n"); if (!is_valid_ether_addr(mac_addr)) { u_int32_t i; debug("Did not find a valid mac address in e-fuse. " "Trying the one present in EEPROM\n"); for (i = 0; i < HDR_ETH_ALEN; i++) mac_addr[i] = header.mac_addr[0][i]; } if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("ethaddr", mac_addr); else { printf("Caution: Using hardcoded mac address. " "Set <ethaddr> variable to overcome this.\n"); } } if (board_is_bone()) { writel(MII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; } else { writel(RGMII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; } rv = cpsw_register(&cpsw_data); if (rv < 0) { ret = -1; printf("Error %d registering CPSW switch\n", rv); } #endif #if defined(CONFIG_USB_ETHER) && \ (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETH_SUPPORT)) if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("usbnet_devaddr", mac_addr); /* * SPL does not call arch_misc_init and the ROM only supports using * USB0 for boot. */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETH_SUPPORT) rv = musb_register(&otg0_plat, &otg0_board_data, (void *)AM335X_USB0_OTG_BASE); if (rv < 0) { printf("Error %d registering MUSB device\n", rv); return -1; } #endif rv = usb_eth_initialize(bis); if (rv < 0) { printf("Error %d registering USB_ETHER\n", rv); return -1; } #endif return ret; }
int board_eth_init(bd_t *bis) { int ret; uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; uint32_t ctrl_val; int i; u64 mac1, mac2; u8 mac_addr1[6], mac_addr2[6]; int num_macs; /* try reading mac address from efuse */ mac_lo = readl((*ctrl)->control_core_mac_id_0_lo); mac_hi = readl((*ctrl)->control_core_mac_id_0_hi); mac_addr[0] = (mac_hi & 0xFF0000) >> 16; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = mac_hi & 0xFF; mac_addr[3] = (mac_lo & 0xFF0000) >> 16; mac_addr[4] = (mac_lo & 0xFF00) >> 8; mac_addr[5] = mac_lo & 0xFF; if (!getenv("ethaddr")) { printf("<ethaddr> not set. Validating first E-fuse MAC\n"); if (is_valid_ethaddr(mac_addr)) eth_setenv_enetaddr("ethaddr", mac_addr); } mac_lo = readl((*ctrl)->control_core_mac_id_1_lo); mac_hi = readl((*ctrl)->control_core_mac_id_1_hi); mac_addr[0] = (mac_hi & 0xFF0000) >> 16; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = mac_hi & 0xFF; mac_addr[3] = (mac_lo & 0xFF0000) >> 16; mac_addr[4] = (mac_lo & 0xFF00) >> 8; mac_addr[5] = mac_lo & 0xFF; if (!getenv("eth1addr")) { if (is_valid_ethaddr(mac_addr)) eth_setenv_enetaddr("eth1addr", mac_addr); } ctrl_val = readl((*ctrl)->control_core_control_io1) & (~0x33); ctrl_val |= 0x22; writel(ctrl_val, (*ctrl)->control_core_control_io1); /* The phy address for the AM572x IDK are different than x15 */ if (board_is_am572x_idk()) { cpsw_data.slave_data[0].phy_addr = 0; cpsw_data.slave_data[1].phy_addr = 1; } ret = cpsw_register(&cpsw_data); if (ret < 0) printf("Error %d registering CPSW switch\n", ret); /* * Export any Ethernet MAC addresses from EEPROM. * On AM57xx the 2 MAC addresses define the address range */ board_ti_get_eth_mac_addr(0, mac_addr1); board_ti_get_eth_mac_addr(1, mac_addr2); if (is_valid_ethaddr(mac_addr1) && is_valid_ethaddr(mac_addr2)) { mac1 = mac_to_u64(mac_addr1); mac2 = mac_to_u64(mac_addr2); /* must contain an address range */ num_macs = mac2 - mac1 + 1; /* <= 50 to protect against user programming error */ if (num_macs > 0 && num_macs <= 50) { for (i = 0; i < num_macs; i++) { u64_to_mac(mac1 + i, mac_addr); if (is_valid_ethaddr(mac_addr)) { eth_setenv_enetaddr_by_index("eth", i + 2, mac_addr); } } } } return ret; }
int board_eth_init(bd_t *bis) { int rv, n = 0; uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; /* try reading mac address from efuse */ mac_lo = readl(&cdev->macid0l); mac_hi = readl(&cdev->macid0h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) if (!env_get("ethaddr")) { printf("<ethaddr> not set. Validating first E-fuse MAC\n"); if (is_valid_ethaddr(mac_addr)) eth_env_set_enetaddr("ethaddr", mac_addr); } #ifdef CONFIG_DRIVER_TI_CPSW mac_lo = readl(&cdev->macid1l); mac_hi = readl(&cdev->macid1h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; if (!env_get("eth1addr")) { if (is_valid_ethaddr(mac_addr)) eth_env_set_enetaddr("eth1addr", mac_addr); } writel(MII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; rv = cpsw_register(&cpsw_data); if (rv < 0) printf("Error %d registering CPSW switch\n", rv); else n += rv; #endif /* * * CPSW RGMII Internal Delay Mode is not supported in all PVT * operating points. So we must set the TX clock delay feature * in the AR8051 PHY. Since we only support a single ethernet * device in U-Boot, we only do this for the first instance. */ #define AR8051_PHY_DEBUG_ADDR_REG 0x1d #define AR8051_PHY_DEBUG_DATA_REG 0x1e #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 #define AR8051_RGMII_TX_CLK_DLY 0x100 #endif #if defined(CONFIG_USB_ETHER) && \ (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER)) if (is_valid_ether_addr(mac_addr)) eth_env_set_enetaddr("usbnet_devaddr", mac_addr); rv = usb_eth_initialize(bis); if (rv < 0) printf("Error %d registering USB_ETHER\n", rv); else n += rv; #endif return n; }
int board_eth_init(bd_t *bis) { int rv, n = 0; uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; __maybe_unused struct am335x_baseboard_id header; /* try reading mac address from efuse */ mac_lo = readl(&cdev->macid0l); mac_hi = readl(&cdev->macid0h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) if (!getenv("ethaddr")) { printf("<ethaddr> not set. Validating first E-fuse MAC\n"); if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("ethaddr", mac_addr); } #ifdef CONFIG_DRIVER_TI_CPSW mac_lo = readl(&cdev->macid1l); mac_hi = readl(&cdev->macid1h); mac_addr[0] = mac_hi & 0xFF; mac_addr[1] = (mac_hi & 0xFF00) >> 8; mac_addr[2] = (mac_hi & 0xFF0000) >> 16; mac_addr[3] = (mac_hi & 0xFF000000) >> 24; mac_addr[4] = mac_lo & 0xFF; mac_addr[5] = (mac_lo & 0xFF00) >> 8; if (!getenv("eth1addr")) { if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("eth1addr", mac_addr); } if (read_eeprom(&header) < 0) puts("Could not get board ID.\n"); if (board_is_catchwire(&header) || board_is_luna(&header) || board_is_kalitap(&header)) { writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; } else { writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; } rv = cpsw_register(&cpsw_data); if (rv < 0) printf("Error %d registering CPSW switch\n", rv); else n += rv; #endif #endif #if defined(CONFIG_USB_ETHER) && \ (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("usbnet_devaddr", mac_addr); rv = usb_eth_initialize(bis); if (rv < 0) printf("Error %d registering USB_ETHER\n", rv); else n += rv; #endif return n; }
static void board_init_ddr(void) { struct emif_regs rut_ddr3_emif_reg_data = { .sdram_config = 0x61C04AB2, .sdram_tim1 = 0x0888A39B, .sdram_tim2 = 0x26337FDA, .sdram_tim3 = 0x501F830F, .emif_ddr_phy_ctlr_1 = 0x6, .zq_config = 0x50074BE4, .ref_ctrl = 0x93B, }; struct ddr_data rut_ddr3_data = { .datardsratio0 = 0x3b, .datawdsratio0 = 0x85, .datafwsratio0 = 0x100, .datawrsratio0 = 0xc1, }; struct cmd_control rut_ddr3_cmd_ctrl_data = { .cmd0csratio = 0x40, .cmd0iclkout = 1, .cmd1csratio = 0x40, .cmd1iclkout = 1, .cmd2csratio = 0x40, .cmd2iclkout = 1, }; config_ddr(DDR_PLL_FREQ, RUT_IOCTRL_VAL, &rut_ddr3_data, &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0); } static void spl_siemens_board_init(void) { return; } #endif /* if def CONFIG_SPL_BUILD */ #if defined(CONFIG_DRIVER_TI_CPSW) static void cpsw_control(int enabled) { /* VTP can be added here */ return; } static struct cpsw_slave_data cpsw_slaves[] = { { .slave_reg_ofs = 0x208, .sliver_reg_ofs = 0xd80, .phy_addr = 1, .phy_if = PHY_INTERFACE_MODE_RMII, }, { .slave_reg_ofs = 0x308, .sliver_reg_ofs = 0xdc0, .phy_addr = 0, .phy_if = PHY_INTERFACE_MODE_RMII, }, }; static struct cpsw_platform_data cpsw_data = { .mdio_base = CPSW_MDIO_BASE, .cpsw_base = CPSW_BASE, .mdio_div = 0xff, .channels = 8, .cpdma_reg_ofs = 0x800, .slaves = 1, .slave_data = cpsw_slaves, .ale_reg_ofs = 0xd00, .ale_entries = 1024, .host_port_reg_ofs = 0x108, .hw_stats_reg_ofs = 0x900, .bd_ram_ofs = 0x2000, .mac_control = (1 << 5), .control = cpsw_control, .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, }; #if defined(CONFIG_DRIVER_TI_CPSW) || \ (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) int board_eth_init(bd_t *bis) { struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; int n = 0; int rv; #ifndef CONFIG_SPL_BUILD factoryset_setenv(); #endif /* Set rgmii mode and enable rmii clock to be sourced from chip */ writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel); rv = cpsw_register(&cpsw_data); if (rv < 0) printf("Error %d registering CPSW switch\n", rv); else n += rv; return n; } #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ #if defined(CONFIG_HW_WATCHDOG) static bool hw_watchdog_init_done; static int hw_watchdog_trigger_level; void hw_watchdog_reset(void) { if (!hw_watchdog_init_done) return; hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1; gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level); } void hw_watchdog_init(void) { gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger"); gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level); hw_watchdog_reset(); hw_watchdog_init_done = 1; } #endif /* defined(CONFIG_HW_WATCHDOG) */ #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) static struct da8xx_panel lcd_panels[] = { /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */ [0] = { .name = "KWH043MC17-F01", .width = 480, .height = 800, .hfp = 50, /* no spec, "don't care" values */ .hbp = 50, .hsw = 50, .vfp = 50, .vbp = 50, .vsw = 50, .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */ .invert_pxl_clk = 1, },
int board_eth_init(bd_t *bis) { int ecode, rv, n; uint8_t mac_addr[6]; struct board_eeconfig header; __maybe_unused enum board_type board; /* Default manufacturing address; used when no EE or invalid */ n = 0; mac_addr[0] = 0; mac_addr[1] = 0x20; mac_addr[2] = 0x18; mac_addr[3] = 0x1C; mac_addr[4] = 0x00; mac_addr[5] = 0x01; ecode = read_eeprom(&header); /* if we have a valid EE, get mac address from there */ if ((ecode == 0) && is_valid_ethaddr((const u8 *)&header.mac_addr[0][0])) { memcpy(mac_addr, (const void *)&header.mac_addr[0][0], 6); } #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) if (!getenv("ethaddr")) { printf("<ethaddr> not set. Validating first E-fuse MAC\n"); if (is_valid_ethaddr(mac_addr)) eth_setenv_enetaddr("ethaddr", mac_addr); } #ifdef CONFIG_DRIVER_TI_CPSW board = get_board_type(false); /* Rev.A uses 10/100 PHY in mii mode */ if (board == BAV335A) { writel(MII_MODE_ENABLE, &cdev->miisel); cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII; cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII; } /* Rev.B (default) uses GB PHY in rmii mode */ else { writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; } rv = cpsw_register(&cpsw_data); if (rv < 0) printf("Error %d registering CPSW switch\n", rv); else n += rv; #endif #endif return n; }