static void write(u32 addr,u8 data)
{
switch(addr & 0xF000) {
case 0x8000:
prg[0] = data;
break;
case 0x9000:
break;
case 0xA000:
break;
case 0xB000:
switch(map[addr & 3]) {
case 0:
case 1:
case 2:
break;
case 3:
mirror = data & 0xC;
break;
}
break;
case 0xC000:
prg[1] = data;
break;
case 0xD000:
chr[map[addr & 3]] = data;
break;
case 0xE000:
chr[map[addr & 3] + 4] = data;
break;
case 0xF000:
switch(map[addr & 3]) {
case 0:
irqlatch = data;
break;
case 1:
irqcontrol = data;
if(data & 2) {
irqcounter = irqlatch;
irqprescaler = 341;
}
cpu_clear_irq(IRQ_MAPPER);
break;
case 2:
cpu_clear_irq(IRQ_MAPPER);
irqcontrol |= (irqcontrol & 1) << 1;
break;
}
break;
}
sync();
}
static void write(u32 addr,u8 data)
{
switch(addr & 0xF000) {
case 0x8000: irqlatch = (irqlatch & 0xFFF0) | ((data & 0xF) << 0); break;
case 0x9000: irqlatch = (irqlatch & 0xFF0F) | ((data & 0xF) << 4); break;
case 0xA000: irqlatch = (irqlatch & 0xF0FF) | ((data & 0xF) << 8); break;
case 0xB000: irqlatch = (irqlatch & 0x0FFF) | ((data & 0xF) << 12); break;
case 0xC000:
irqenable = data & 7;
if(irqenable & 2)
irqcounter = irqlatch;
cpu_clear_irq(IRQ_MAPPER);
break;
case 0xD000:
if(irqenable & 1)
irqenable |= 2;
else
irqenable &= ~2;
cpu_clear_irq(IRQ_MAPPER);
break;
case 0xE000:
control = data & 0xF;
break;
case 0xF000:
switch(control) {
case 1:
case 2:
case 3:
case 4:
prg[control - 1] = (prg[control - 1] & 0x10) | (data & 0xF);
break;
}
switch(addr & 0xFC00) {
case 0xF000:
prg[addr & 3] &= 0xF;
prg[addr & 3] |= (data & 0x10);
break;
case 0xF400:
break;
case 0xF800:
mirror = data & 1;
break;
case 0xFC00:
chr[addr & 7] = data;
break;
}
sync();
break;
}
}
static void sync()
{
static u8 oldreg1 = 0x10;
u8 reg1 = mmc1_getlowchr();
mmc1_syncmirror();
mmc1_syncsram();
mem_setvram8(0,0);
if(reg1 & 0x10) {
irqenabled = 0;
irqcounter = 0;
cpu_clear_irq(IRQ_MAPPER);
}
else
irqenabled = 1;
if(prglock) {
mem_setprg32(8,0);
if((oldreg1 & 0x10) == 0 && (reg1 & 0x10) == 0x10)
prglock = 0;
}
else {
if(reg1 & 8)
mmc1_syncprg(7,8);
else
mem_setprg32(8,(reg1 >> 1) & 3);
}
oldreg1 = reg1;
}
