static int mx51_suspend_enter(suspend_state_t state) { if (gpc_dvfs_clk == NULL) gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk"); /* gpc clock is needed for SRPG */ clk_enable(gpc_dvfs_clk); switch (state) { case PM_SUSPEND_MEM: mxc_cpu_lp_set(STOP_POWER_OFF); break; case PM_SUSPEND_STANDBY: mxc_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF); break; default: return -EINVAL; } if (tzic_enable_wake(0) != 0) return -EAGAIN; if (state == PM_SUSPEND_MEM) { cpu_do_suspend_workaround(); /*clear the EMPGC0/1 bits */ __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); } else { if ((mxc_cpu_is_rev(CHIP_REV_2_0)) < 0) { /* do cpu_idle_workaround */ u32 l2_iram_addr = IDLE_IRAM_BASE_ADDR; if (!iram_ready) return 0; if (l2_iram_addr > 0x1FFE8000) cpu_cortexa8_do_idle(IO_ADDRESS(l2_iram_addr)); } else { cpu_do_idle(); } } clk_disable(gpc_dvfs_clk); return 0; }
/*! * This function puts the CPU into idle mode. It is called by default_idle() * in process.c file. */ void arch_idle(void) { if (likely(!mxc_jtag_enabled)) { if (gpc_dvfs_clk == NULL) gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk"); /* gpc clock is needed for SRPG */ clk_enable(gpc_dvfs_clk); mxc_cpu_lp_set(arch_idle_mode); if ((mxc_cpu_is_rev(CHIP_REV_2_0)) < 0) { u32 l2_iram_addr = IDLE_IRAM_BASE_ADDR; if (!iram_ready) return; if (l2_iram_addr > 0x1FFE8000) cpu_cortexa8_do_idle(IO_ADDRESS(l2_iram_addr)); } else { cpu_do_idle(); } clk_disable(gpc_dvfs_clk); } }