static struct os *
os_alloc(int n_cpus)
{
struct os *os;
int i;
os = halloc(sizeof(*os));
if (os == NULL)
return NULL;
memset(os, 0, sizeof (*os));
for (i = 0; i < n_cpus; i++) {
os->cpu[i] = cpu_create(os, i);
if (os->cpu[i] == NULL)
goto unwind;
os->installed_cpus++;
}
return os;
/* *INDENT-OFF* */
unwind:
/* *INDENT-ON* */
if (os != NULL)
os_free(os);
return NULL;
}
SPARCCPU *sparc64_cpu_devinit(const char *cpu_type, uint64_t prom_addr)
{
SPARCCPU *cpu;
CPUSPARCState *env;
ResetData *reset_info;
uint32_t tick_frequency = 100 * 1000000;
uint32_t stick_frequency = 100 * 1000000;
uint32_t hstick_frequency = 100 * 1000000;
cpu = SPARC_CPU(cpu_create(cpu_type));
qdev_init_gpio_in_named(DEVICE(cpu), sparc64_cpu_set_ivec_irq,
"ivec-irq", IVEC_MAX);
env = &cpu->env;
env->tick = cpu_timer_create("tick", cpu, tick_irq,
tick_frequency, TICK_INT_DIS,
TICK_NPT_MASK);
env->stick = cpu_timer_create("stick", cpu, stick_irq,
stick_frequency, TICK_INT_DIS,
TICK_NPT_MASK);
env->hstick = cpu_timer_create("hstick", cpu, hstick_irq,
hstick_frequency, TICK_INT_DIS,
TICK_NPT_MASK);
reset_info = g_malloc0(sizeof(ResetData));
reset_info->cpu = cpu;
reset_info->prom_addr = prom_addr;
qemu_register_reset(main_cpu_reset, reset_info);
return cpu;
}
/*
* Thread system initialization.
*/
void
thread_bootstrap(void)
{
cpuarray_init(&allcpus);
/*
* Create the cpu structure for the bootup CPU, the one we're
* currently running on. Assume the hardware number is 0; that
* might be updated later by mainbus-type code. This also
* creates a thread structure for the first thread, the one
* that's already implicitly running when the kernel is
* started from the bootloader.
*/
KASSERT(CURCPU_EXISTS() == false);
(void)cpu_create(0);
KASSERT(CURCPU_EXISTS() == true);
/* cpu_create() should also have set t_proc. */
KASSERT(curcpu != NULL);
KASSERT(curthread != NULL);
KASSERT(curthread->t_proc != NULL);
KASSERT(curthread->t_proc == kproc);
/* Done */
}
//---------------funcion encargado de recibir conexiones de CPUs -------------------------
int recibir_conexion(){
int socketCpu;
int id;
socketCpu = crearSocketParaAceptarSolicitudes(socketEscucha); //
recibirMensajeCompleto(socketCpu, &id, sizeof(int));// recibo id de CPU
pthread_mutex_lock(&cpuss);
list_add(CPUs, cpu_create(id,1,socketCpu)); // guardo en la lista
pthread_mutex_unlock(&cpuss);
enviarMensaje(socketCpu,&quantum,sizeof(quantum)); // le mando el quantum, que es un int
FD_SET(socketCpu, &master); // Agrega socketCpu al master set
if (socketCpu > fdmax) { // es el mayor
fdmax = socketCpu; // guardo el mayor
}
read_fds = master; // actualizo el temporal
sem_post(&solicitud_cpuLibre); // desperta a al hilo "ejecutar_proceso"
return 0;
}
emu_t*
emu_create(void)
{
emu_t * emu;
emu = (emu_t*)calloc(sizeof(emu_t), 1);
emu->cpu = cpu_create(emu);
emu->ppu = ppu_create(emu);
return emu;
}
computer_t *computer_create ()
{
computer_t *computer = (computer_t*) malloc (sizeof (computer_t));
computer->cpu = cpu_create (computer);
computer->memory = memory_create (computer);
computer->devices = device_list_create ();
graphic_card_register (computer);
return computer;
}
static void nios2_generic_nommu_init(MachineState *machine)
{
Nios2CPU *cpu;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *phys_tcm = g_new(MemoryRegion, 1);
MemoryRegion *phys_tcm_alias = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram_alias = g_new(MemoryRegion, 1);
ram_addr_t tcm_base = 0x0;
ram_addr_t tcm_size = 0x1000; /* 1 kiB, but QEMU limit is 4 kiB */
ram_addr_t ram_base = 0x10000000;
ram_addr_t ram_size = 0x08000000;
/* Physical TCM (tb_ram_1k) with alias at 0xc0000000 */
memory_region_init_ram(phys_tcm, NULL, "nios2.tcm", tcm_size,
&error_abort);
memory_region_init_alias(phys_tcm_alias, NULL, "nios2.tcm.alias",
phys_tcm, 0, tcm_size);
memory_region_add_subregion(address_space_mem, tcm_base, phys_tcm);
memory_region_add_subregion(address_space_mem, 0xc0000000 + tcm_base,
phys_tcm_alias);
/* Physical DRAM with alias at 0xc0000000 */
memory_region_init_ram(phys_ram, NULL, "nios2.ram", ram_size,
&error_abort);
memory_region_init_alias(phys_ram_alias, NULL, "nios2.ram.alias",
phys_ram, 0, ram_size);
memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
memory_region_add_subregion(address_space_mem, 0xc0000000 + ram_base,
phys_ram_alias);
cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU));
/* Remove MMU */
cpu->mmu_present = false;
/* Reset vector is the first 32 bytes of RAM. */
cpu->reset_addr = ram_base;
/* The interrupt vector comes right after reset. */
cpu->exception_addr = ram_base + 0x20;
/*
* The linker script does have a TLB miss memory region declared,
* but this should never be used with no MMU.
*/
cpu->fast_tlb_miss_addr = 0x7fff400;
nios2_load_kernel(cpu, ram_base, ram_size, machine->initrd_filename,
BINARY_DEVICE_TREE_FILE, NULL);
}
static void openrisc_sim_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
const char *kernel_filename = machine->kernel_filename;
OpenRISCCPU *cpu = NULL;
MemoryRegion *ram;
qemu_irq *cpu_irqs[2];
qemu_irq serial_irq;
int n;
for (n = 0; n < smp_cpus; n++) {
cpu = OPENRISC_CPU(cpu_create(machine->cpu_type));
if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition!\n");
exit(1);
}
cpu_openrisc_pic_init(cpu);
cpu_irqs[n] = (qemu_irq *) cpu->env.irq;
cpu_openrisc_clock_init(cpu);
qemu_register_reset(main_cpu_reset, cpu);
}
ram = g_malloc(sizeof(*ram));
memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal);
memory_region_add_subregion(get_system_memory(), 0, ram);
if (nd_table[0].used) {
openrisc_sim_net_init(0x92000000, 0x92000400, smp_cpus,
cpu_irqs, 4, nd_table);
}
if (smp_cpus > 1) {
openrisc_sim_ompic_init(0x98000000, smp_cpus, cpu_irqs, 1);
serial_irq = qemu_irq_split(cpu_irqs[0][2], cpu_irqs[1][2]);
} else {
serial_irq = cpu_irqs[0][2];
}
serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq,
115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
openrisc_load_kernel(ram_size, kernel_filename);
}
static void moxiesim_init(MachineState *machine)
{
MoxieCPU *cpu = NULL;
ram_addr_t ram_size = machine->ram_size;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
CPUMoxieState *env;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *rom = g_new(MemoryRegion, 1);
hwaddr ram_base = 0x200000;
LoaderParams loader_params;
/* Init CPUs. */
cpu = MOXIE_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
qemu_register_reset(main_cpu_reset, cpu);
/* Allocate RAM. */
memory_region_init_ram(ram, NULL, "moxiesim.ram", ram_size, &error_fatal);
memory_region_add_subregion(address_space_mem, ram_base, ram);
memory_region_init_ram(rom, NULL, "moxie.rom", FIRMWARE_SIZE, &error_fatal);
memory_region_add_subregion(get_system_memory(), FIRMWARE_BASE, rom);
if (kernel_filename) {
loader_params.ram_size = ram_size;
loader_params.kernel_filename = kernel_filename;
loader_params.kernel_cmdline = kernel_cmdline;
loader_params.initrd_filename = initrd_filename;
load_kernel(cpu, &loader_params);
}
if (bios_name) {
if (load_image_targphys(bios_name, FIRMWARE_BASE, FIRMWARE_SIZE) < 0) {
error_report("Failed to load firmware '%s'", bios_name);
}
}
/* A single 16450 sits at offset 0x3f8. */
if (serial_hds[0]) {
serial_mm_init(address_space_mem, 0x3f8, 0, env->irq[4],
8000000/16, serial_hds[0], DEVICE_LITTLE_ENDIAN);
}
}
/*
* Find and create secondary CPUs.
*/
void
lamebus_find_cpus(struct lamebus_softc *lamebus)
{
uint32_t cpumask, self, bit, val;
unsigned i, numcpus, bootcpu;
unsigned hwnum[32];
cpumask = read_ctl_register(lamebus, CTLREG_CPUS);
self = read_ctl_register(lamebus, CTLREG_SELF);
numcpus = 0;
bootcpu = 0;
for (i=0; i<32; i++) {
bit = (uint32_t)1 << i;
if ((cpumask & bit) != 0) {
if (self & bit) {
bootcpu = numcpus;
curcpu->c_hardware_number = i;
}
hwnum[numcpus] = i;
numcpus++;
}
}
for (i=0; i<numcpus; i++) {
if (i != bootcpu) {
cpu_create(hwnum[i]);
}
}
/*
* By default, route all interrupts only to the boot cpu. We
* could be arbitrarily more elaborate, up to things like
* dynamic load balancing.
*/
for (i=0; i<numcpus; i++) {
if (i != bootcpu) {
val = 0;
}
else {
val = 0xffffffff;
}
write_ctlcpu_register(lamebus, hwnum[i], CTLCPU_CIRQE, val);
}
}
/*
* Thread system initialization.
*/
void
thread_bootstrap(void)
{
struct cpu *bootcpu;
struct thread *bootthread;
cpuarray_init(&allcpus);
/*
* Create the cpu structure for the bootup CPU, the one we're
* currently running on. Assume the hardware number is 0; that
* might be updated later by mainbus-type code. This also
* creates a thread structure for the first thread, the one
* that's already implicitly running when the kernel is
* started from the bootloader.
*/
bootcpu = cpu_create(0);
bootthread = bootcpu->c_curthread;
/*
* Initializing curcpu and curthread is machine-dependent
* because either of curcpu and curthread might be defined in
* terms of the other.
*/
INIT_CURCPU(bootcpu, bootthread);
/*
* Now make sure both t_cpu and c_curthread are set. This
* might be partially redundant with INIT_CURCPU depending on
* how things are defined.
*/
curthread->t_cpu = curcpu;
curcpu->c_curthread = curthread;
/* cpu_create() should have set t_proc. */
KASSERT(curthread->t_proc != NULL);
/* Initialize allwchans */
spinlock_init(&allwchans_lock);
wchanarray_init(&allwchans);
/* Done */
}
static void puv3_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
const char *kernel_filename = machine->kernel_filename;
const char *initrd_filename = machine->initrd_filename;
CPUUniCore32State *env;
UniCore32CPU *cpu;
if (initrd_filename) {
error_report("Please use kernel built-in initramdisk");
exit(1);
}
cpu = UNICORE32_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
puv3_soc_init(env);
puv3_board_init(env, ram_size);
puv3_load_kernel(kernel_filename);
}
static void mips_jazz_init(MachineState *machine,
enum jazz_model_e jazz_model)
{
MemoryRegion *address_space = get_system_memory();
char *filename;
int bios_size, n;
MIPSCPU *cpu;
CPUClass *cc;
CPUMIPSState *env;
qemu_irq *i8259;
rc4030_dma *dmas;
IOMMUMemoryRegion *rc4030_dma_mr;
MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
MemoryRegion *isa_io = g_new(MemoryRegion, 1);
MemoryRegion *rtc = g_new(MemoryRegion, 1);
MemoryRegion *i8042 = g_new(MemoryRegion, 1);
MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
NICInfo *nd;
DeviceState *dev, *rc4030;
SysBusDevice *sysbus;
ISABus *isa_bus;
ISADevice *pit;
DriveInfo *fds[MAX_FD];
qemu_irq esp_reset, dma_enable;
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
MemoryRegion *bios2 = g_new(MemoryRegion, 1);
/* init CPUs */
cpu = MIPS_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
qemu_register_reset(main_cpu_reset, cpu);
/* Chipset returns 0 in invalid reads and do not raise data exceptions.
* However, we can't simply add a global memory region to catch
* everything, as memory core directly call unassigned_mem_read/write
* on some invalid accesses, which call do_unassigned_access on the
* CPU, which raise an exception.
* Handle that case by hijacking the do_unassigned_access method on
* the CPU, and do not raise exceptions for data access. */
cc = CPU_GET_CLASS(cpu);
real_do_unassigned_access = cc->do_unassigned_access;
cc->do_unassigned_access = mips_jazz_do_unassigned_access;
/* allocate RAM */
memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram",
machine->ram_size);
memory_region_add_subregion(address_space, 0, ram);
memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
&error_fatal);
memory_region_set_readonly(bios, true);
memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
0, MAGNUM_BIOS_SIZE);
memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
/* load the BIOS image. */
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
bios_size = load_image_targphys(filename, 0xfff00000LL,
MAGNUM_BIOS_SIZE);
g_free(filename);
} else {
bios_size = -1;
}
if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
error_report("Could not load MIPS bios '%s'", bios_name);
exit(1);
}
/* Init CPU internal devices */
cpu_mips_irq_init_cpu(cpu);
cpu_mips_clock_init(cpu);
/* Chipset */
rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
sysbus = SYS_BUS_DEVICE(rc4030);
sysbus_connect_irq(sysbus, 0, env->irq[6]);
sysbus_connect_irq(sysbus, 1, env->irq[3]);
memory_region_add_subregion(address_space, 0x80000000,
sysbus_mmio_get_region(sysbus, 0));
memory_region_add_subregion(address_space, 0xf0000000,
sysbus_mmio_get_region(sysbus, 1));
memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
/* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
memory_region_add_subregion(address_space, 0x90000000, isa_io);
memory_region_add_subregion(address_space, 0x91000000, isa_mem);
isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);
/* ISA devices */
i8259 = i8259_init(isa_bus, env->irq[4]);
isa_bus_irqs(isa_bus, i8259);
DMA_init(isa_bus, 0);
pit = pit_init(isa_bus, 0x40, 0, NULL);
pcspk_init(isa_bus, pit);
/* Video card */
switch (jazz_model) {
case JAZZ_MAGNUM:
dev = qdev_create(NULL, "sysbus-g364");
qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sysbus, 0, 0x60080000);
sysbus_mmio_map(sysbus, 1, 0x40000000);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
{
/* Simple ROM, so user doesn't have to provide one */
MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000,
&error_fatal);
memory_region_set_readonly(rom_mr, true);
uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
memory_region_add_subregion(address_space, 0x60000000, rom_mr);
rom[0] = 0x10; /* Mips G364 */
}
break;
case JAZZ_PICA61:
isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
break;
default:
break;
}
/* Network controller */
for (n = 0; n < nb_nics; n++) {
nd = &nd_table[n];
if (!nd->model)
nd->model = g_strdup("dp83932");
if (strcmp(nd->model, "dp83932") == 0) {
qemu_check_nic_model(nd, "dp83932");
dev = qdev_create(NULL, "dp8393x");
qdev_set_nic_properties(dev, nd);
qdev_prop_set_uint8(dev, "it_shift", 2);
qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr);
qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sysbus, 0, 0x80001000);
sysbus_mmio_map(sysbus, 1, 0x8000b000);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
break;
} else if (is_help_option(nd->model)) {
fprintf(stderr, "qemu: Supported NICs: dp83932\n");
exit(1);
} else {
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
exit(1);
}
}
/* SCSI adapter */
esp_init(0x80002000, 0,
rc4030_dma_read, rc4030_dma_write, dmas[0],
qdev_get_gpio_in(rc4030, 5), &esp_reset, &dma_enable);
/* Floppy */
for (n = 0; n < MAX_FD; n++) {
fds[n] = drive_get(IF_FLOPPY, 0, n);
}
/* FIXME: we should enable DMA with a custom IsaDma device */
fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds);
/* Real time clock */
rtc_init(isa_bus, 1980, NULL);
memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
memory_region_add_subregion(address_space, 0x80004000, rtc);
/* Keyboard (i8042) */
i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
i8042, 0x1000, 0x1);
memory_region_add_subregion(address_space, 0x80005000, i8042);
/* Serial ports */
if (serial_hds[0]) {
serial_mm_init(address_space, 0x80006000, 0,
qdev_get_gpio_in(rc4030, 8), 8000000/16,
serial_hds[0], DEVICE_NATIVE_ENDIAN);
}
if (serial_hds[1]) {
serial_mm_init(address_space, 0x80007000, 0,
qdev_get_gpio_in(rc4030, 9), 8000000/16,
serial_hds[1], DEVICE_NATIVE_ENDIAN);
}
/* Parallel port */
if (parallel_hds[0])
parallel_mm_init(address_space, 0x80008000, 0,
qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);
/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
/* NVRAM */
dev = qdev_create(NULL, "ds1225y");
qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sysbus, 0, 0x80009000);
/* LED indicator */
sysbus_create_simple("jazz-led", 0x8000f000, NULL);
}
/* Initialize the C3725 Platform */
static int c3725_init_platform(c3725_t *router)
{
vm_instance_t *vm = router->vm;
cpu_mips_t *cpu;
cpu_gen_t *gen;
vm_obj_t *obj;
/* Copy config register setup into "active" config register */
vm->conf_reg = vm->conf_reg_setup;
/* Create Console and AUX ports */
vm_init_vtty(vm);
/* Create a CPU group */
vm->cpu_group = cpu_group_create("System CPU");
/* Initialize the virtual MIPS processor */
if (!(gen = cpu_create(vm,CPU_TYPE_MIPS64,0))) {
vm_error(vm,"unable to create CPU!\n");
return(-1);
}
cpu = CPU_MIPS64(gen);
/* Add this CPU to the system CPU group */
cpu_group_add(vm->cpu_group,gen);
vm->boot_cpu = gen;
/* Initialize the IRQ routing vectors */
vm->set_irq = mips64_vm_set_irq;
vm->clear_irq = mips64_vm_clear_irq;
/* Mark the Network IO interrupt as high priority */
cpu->irq_idle_preempt[C3725_NETIO_IRQ] = TRUE;
cpu->irq_idle_preempt[C3725_GT96K_IRQ] = TRUE;
cpu->irq_idle_preempt[C3725_DUART_IRQ] = TRUE;
/* Copy some parameters from VM to CPU (idle PC, ...) */
cpu->idle_pc = vm->idle_pc;
if (vm->timer_irq_check_itv)
cpu->timer_irq_check_itv = vm->timer_irq_check_itv;
/* Remote emulator control */
dev_remote_control_init(vm,0x16000000,0x1000);
/* Specific Storage Area (SSA) */
dev_ram_init(vm,"ssa",TRUE,FALSE,NULL,FALSE,0x16001000ULL,0x7000);
/* IO FPGA */
if (dev_c3725_iofpga_init(router,C3725_IOFPGA_ADDR,0x40000) == -1)
return(-1);
if (!(obj = vm_object_find(router->vm,"io_fpga")))
return(-1);
router->iofpga_data = obj->data;
#if 0
/* PCI IO space */
if (!(vm->pci_io_space = pci_io_data_init(vm,C3725_PCI_IO_ADDR)))
return(-1);
#endif
/* Initialize the chassis */
if (c3725_init(router) == -1)
return(-1);
/* Initialize RAM */
vm_ram_init(vm,0x00000000ULL);
/* Initialize ROM (as a Flash) */
if (!(obj = dev_flash_init(vm,"rom",C3725_ROM_ADDR,vm->rom_size*1048576)))
return(-1);
dev_flash_copy_data(obj,0,mips64_microcode,mips64_microcode_len);
c3725_nvram_check_empty_config(vm);
/* Byte swapping */
dev_bswap_init(vm,"mem_bswap",C3725_BSWAP_ADDR,1024*1048576,0x00000000ULL);
/* Initialize the NS16552 DUART */
dev_ns16552_init(vm,C3725_DUART_ADDR,0x1000,3,C3725_DUART_IRQ,
vm->vtty_con,vm->vtty_aux);
/* PCMCIA Slot 0 */
dev_pcmcia_disk_init(vm,"slot0",C3725_SLOT0_ADDR,0x200000,
vm->pcmcia_disk_size[0],1);
/* PCMCIA Slot 1 */
dev_pcmcia_disk_init(vm,"slot1",C3725_SLOT1_ADDR,0x200000,
vm->pcmcia_disk_size[1],1);
/* Initialize Network Modules */
if (vm_slot_init_all(vm) == -1)
return(-1);
/* Show device list */
c3725_show_hardware(router);
return(0);
}
int main(int argc, char *argv[])
{
cpu_t *cpu = cpu_create();
uint8_t opcode;
FILE *file = NULL;
char *dump_ram = NULL;
char *dump_flash = NULL;
char **buffer = NULL;
int i;
if(argc != 2 && argc != 4 && argc != 6)
{
puts("usage: fsim <in> [--dumpram|-r <ram filename>] [--dumpflash|-f <flash filename>]");
return EXIT_SUCCESS;
}
for (i = 2; i < argc; i++)
{
if (memcmp("--dumpram", argv[i], 9) == 0 || memcmp("-r", argv[i], 2) == 0)
{
buffer = &dump_ram;
}
else if (memcmp("--dumpflash", argv[i], 11) == 0 || memcmp("-f", argv[i], 2) == 0)
{
buffer = &dump_flash;
}
else if (buffer)
{
*buffer = argv[i];
buffer = NULL;
}
else
{
printf("unknown option \"%s\"\n", argv[i]);
return EXIT_FAILURE;
}
}
if (buffer)
{
puts("Not all options set");
return EXIT_FAILURE;
}
file = fopen(argv[1], "r");
if(!file)
{
printf("could not open file \"%s\"",argv[1]);
return EXIT_FAILURE;
}
fread(cpu->flash, sizeof(cpu->flash), 1, file);
fclose(file);
file = NULL;
printf("First 160 bytes of flash:");
for(i = 0;i < 160; i++) {
if (i % 16 == 0)
{
printf("\n%08x:", i + 0x01000000);
}
if (i % 2 == 0)
{
printf(" ");
}
printf("%02x", cpu->flash[i]);
}
printf("\n\n");
while(!cpu->status)
{
opcode = cpu_step(cpu);
}
switch (cpu->status)
{
case 2:
printf("Illegal opcode \"%02x\"\n", opcode);
break;
case 1:
puts("");
puts("####################");
puts("# ## #");
puts("#### Halted CPU ####");
puts("# ## #");
puts("####################");
puts("");
break;
default:
printf("Unknown exit status %d", cpu->status);
}
puts("Register Dump:");
printf("A = %08x\n", cpu->a);
printf("X = %08x\n", cpu->x);
printf("PC = %08x\n", cpu->pc);
printf("SP = %08x\n", cpu->sp);
printf("z = %01d\n", cpu->z);
printf("n = %01d\n", cpu->n);
printf("i = %01d\n", cpu->i);
printf("if = %02x\n", cpu->interrupt_flags);
printf("iv = %08x\n", cpu->interrupt_vector);
puts("");
dump_stack(cpu, 10);
if (dump_flash)
{
file = fopen(dump_flash, "w");
if(!file)
{
printf("could not open flash file \"%s\"", dump_flash);
} else {
fwrite(cpu->flash, sizeof(cpu->flash), 1, file);
fclose(file);
printf("Dumped flash to \"%s\"\n", dump_flash);
}
}
if (dump_ram)
{
file = fopen(dump_ram, "w");
if(!file)
{
printf("could not open ram file \"%s\"", dump_ram);
} else {
fwrite(cpu->ram, sizeof(cpu->ram), 1, file);
fclose(file);
printf("Dumped ram to \"%s\"\n", dump_ram);
}
}
cpu = cpu_free(cpu);
return 0;
}
static
void mips_r4k_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
char *filename;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios;
MemoryRegion *iomem = g_new(MemoryRegion, 1);
MemoryRegion *isa_io = g_new(MemoryRegion, 1);
MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
int bios_size;
MIPSCPU *cpu;
CPUMIPSState *env;
ResetData *reset_info;
int i;
qemu_irq *i8259;
ISABus *isa_bus;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
DriveInfo *dinfo;
int be;
/* init CPUs */
cpu = MIPS_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
reset_info = g_malloc0(sizeof(ResetData));
reset_info->cpu = cpu;
reset_info->vector = env->active_tc.PC;
qemu_register_reset(main_cpu_reset, reset_info);
/* allocate RAM */
if (ram_size > (256 << 20)) {
error_report("Too much memory for this machine: %dMB, maximum 256MB",
((unsigned int)ram_size / (1 << 20)));
exit(1);
}
memory_region_allocate_system_memory(ram, NULL, "mips_r4k.ram", ram_size);
memory_region_add_subregion(address_space_mem, 0, ram);
memory_region_init_io(iomem, NULL, &mips_qemu_ops, NULL, "mips-qemu", 0x10000);
memory_region_add_subregion(address_space_mem, 0x1fbf0000, iomem);
/* Try to load a BIOS image. If this fails, we continue regardless,
but initialize the hardware ourselves. When a kernel gets
preloaded we also initialize the hardware, since the BIOS wasn't
run. */
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
bios_size = get_image_size(filename);
} else {
bios_size = -1;
}
#ifdef TARGET_WORDS_BIGENDIAN
be = 1;
#else
be = 0;
#endif
if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
bios = g_new(MemoryRegion, 1);
memory_region_init_ram(bios, NULL, "mips_r4k.bios", BIOS_SIZE,
&error_fatal);
memory_region_set_readonly(bios, true);
memory_region_add_subregion(get_system_memory(), 0x1fc00000, bios);
load_image_targphys(filename, 0x1fc00000, BIOS_SIZE);
} else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) {
uint32_t mips_rom = 0x00400000;
if (!pflash_cfi01_register(0x1fc00000, NULL, "mips_r4k.bios", mips_rom,
blk_by_legacy_dinfo(dinfo),
sector_len, mips_rom / sector_len,
4, 0, 0, 0, 0, be)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
}
} else if (!qtest_enabled()) {
/* not fatal */
warn_report("could not load MIPS bios '%s'", bios_name);
}
g_free(filename);
if (kernel_filename) {
loaderparams.ram_size = ram_size;
loaderparams.kernel_filename = kernel_filename;
loaderparams.kernel_cmdline = kernel_cmdline;
loaderparams.initrd_filename = initrd_filename;
reset_info->vector = load_kernel();
}
/* Init CPU internal devices */
cpu_mips_irq_init_cpu(cpu);
cpu_mips_clock_init(cpu);
/* ISA bus: IO space at 0x14000000, mem space at 0x10000000 */
memory_region_init_alias(isa_io, NULL, "isa-io",
get_system_io(), 0, 0x00010000);
memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
memory_region_add_subregion(get_system_memory(), 0x14000000, isa_io);
memory_region_add_subregion(get_system_memory(), 0x10000000, isa_mem);
isa_bus = isa_bus_new(NULL, isa_mem, get_system_io(), &error_abort);
/* The PIC is attached to the MIPS CPU INT0 pin */
i8259 = i8259_init(isa_bus, env->irq[2]);
isa_bus_irqs(isa_bus, i8259);
mc146818_rtc_init(isa_bus, 2000, NULL);
pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
serial_hds_isa_init(isa_bus, 0, MAX_SERIAL_PORTS);
isa_vga_init(isa_bus);
if (nd_table[0].used)
isa_ne2000_init(isa_bus, 0x300, 9, &nd_table[0]);
ide_drive_get(hd, ARRAY_SIZE(hd));
for(i = 0; i < MAX_IDE_BUS; i++)
isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
hd[MAX_IDE_DEVS * i],
hd[MAX_IDE_DEVS * i + 1]);
isa_create_simple(isa_bus, TYPE_I8042);
}
static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
{
#ifdef TARGET_WORDS_BIGENDIAN
int be = 1;
#else
int be = 0;
#endif
MemoryRegion *system_memory = get_system_memory();
XtensaCPU *cpu = NULL;
CPUXtensaState *env = NULL;
MemoryRegion *system_io;
DriveInfo *dinfo;
pflash_t *flash = NULL;
QemuOpts *machine_opts = qemu_get_machine_opts();
const char *kernel_filename = qemu_opt_get(machine_opts, "kernel");
const char *kernel_cmdline = qemu_opt_get(machine_opts, "append");
const char *dtb_filename = qemu_opt_get(machine_opts, "dtb");
const char *initrd_filename = qemu_opt_get(machine_opts, "initrd");
const unsigned system_io_size = 224 * 1024 * 1024;
int n;
for (n = 0; n < smp_cpus; n++) {
cpu = XTENSA_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
env->sregs[PRID] = n;
qemu_register_reset(xtfpga_reset, cpu);
/* Need MMU initialized prior to ELF loading,
* so that ELF gets loaded into virtual addresses
*/
cpu_reset(CPU(cpu));
}
if (env) {
XtensaMemory sysram = env->config->sysram;
sysram.location[0].size = machine->ram_size;
xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom",
system_memory);
xtensa_create_memory_regions(&env->config->instram, "xtensa.instram",
system_memory);
xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom",
system_memory);
xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram",
system_memory);
xtensa_create_memory_regions(&sysram, "xtensa.sysram",
system_memory);
}
system_io = g_malloc(sizeof(*system_io));
memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io",
system_io_size);
memory_region_add_subregion(system_memory, board->io[0], system_io);
if (board->io[1]) {
MemoryRegion *io = g_malloc(sizeof(*io));
memory_region_init_alias(io, NULL, "xtfpga.io.cached",
system_io, 0, system_io_size);
memory_region_add_subregion(system_memory, board->io[1], io);
}
xtfpga_fpga_init(system_io, 0x0d020000);
if (nd_table[0].used) {
xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
xtensa_get_extint(env, 1), nd_table);
}
if (!serial_hds[0]) {
serial_hds[0] = qemu_chr_new("serial0", "null");
}
serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0),
115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
dinfo = drive_get(IF_PFLASH, 0, 0);
if (dinfo) {
flash = xtfpga_flash_init(system_io, board, dinfo, be);
}
/* Use presence of kernel file name as 'boot from SRAM' switch. */
if (kernel_filename) {
uint32_t entry_point = env->pc;
size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */
uint32_t tagptr = env->config->sysrom.location[0].addr +
board->sram_size;
uint32_t cur_tagptr;
BpMemInfo memory_location = {
.type = tswap32(MEMORY_TYPE_CONVENTIONAL),
.start = tswap32(env->config->sysram.location[0].addr),
.end = tswap32(env->config->sysram.location[0].addr +
machine->ram_size),
};
uint32_t lowmem_end = machine->ram_size < 0x08000000 ?
machine->ram_size : 0x08000000;
uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096);
lowmem_end += env->config->sysram.location[0].addr;
cur_lowmem += env->config->sysram.location[0].addr;
xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
system_memory);
if (kernel_cmdline) {
bp_size += get_tag_size(strlen(kernel_cmdline) + 1);
}
if (dtb_filename) {
bp_size += get_tag_size(sizeof(uint32_t));
}
if (initrd_filename) {
bp_size += get_tag_size(sizeof(BpMemInfo));
}
/* Put kernel bootparameters to the end of that SRAM */
tagptr = (tagptr - bp_size) & ~0xff;
cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL);
cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY,
sizeof(memory_location), &memory_location);
if (kernel_cmdline) {
cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE,
strlen(kernel_cmdline) + 1, kernel_cmdline);
}
#ifdef CONFIG_FDT
if (dtb_filename) {
int fdt_size;
void *fdt = load_device_tree(dtb_filename, &fdt_size);
uint32_t dtb_addr = tswap32(cur_lowmem);
if (!fdt) {
error_report("could not load DTB '%s'", dtb_filename);
exit(EXIT_FAILURE);
}
cpu_physical_memory_write(cur_lowmem, fdt, fdt_size);
cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT,
sizeof(dtb_addr), &dtb_addr);
cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4096);
}
#else
if (dtb_filename) {
error_report("could not load DTB '%s': "
"FDT support is not configured in QEMU",
dtb_filename);
exit(EXIT_FAILURE);
}
#endif
if (initrd_filename) {
BpMemInfo initrd_location = { 0 };
int initrd_size = load_ramdisk(initrd_filename, cur_lowmem,
lowmem_end - cur_lowmem);
if (initrd_size < 0) {
initrd_size = load_image_targphys(initrd_filename,
cur_lowmem,
lowmem_end - cur_lowmem);
}
if (initrd_size < 0) {
error_report("could not load initrd '%s'", initrd_filename);
exit(EXIT_FAILURE);
}
initrd_location.start = tswap32(cur_lowmem);
initrd_location.end = tswap32(cur_lowmem + initrd_size);
cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD,
sizeof(initrd_location), &initrd_location);
cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4096);
}
cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL);
env->regs[2] = tagptr;
uint64_t elf_entry;
uint64_t elf_lowaddr;
int success = load_elf(kernel_filename, translate_phys_addr, cpu,
&elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0, 0);
if (success > 0) {
entry_point = elf_entry;
} else {
hwaddr ep;
int is_linux;
success = load_uimage(kernel_filename, &ep, NULL, &is_linux,
translate_phys_addr, cpu);
if (success > 0 && is_linux) {
entry_point = ep;
} else {
error_report("could not load kernel '%s'",
kernel_filename);
exit(EXIT_FAILURE);
}
}
if (entry_point != env->pc) {
uint8_t boot[] = {
#ifdef TARGET_WORDS_BIGENDIAN
0x60, 0x00, 0x08, /* j 1f */
0x00, /* .literal_position */
0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
/* 1: */
0x10, 0xff, 0xfe, /* l32r a0, entry_pc */
0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */
0x0a, 0x00, 0x00, /* jx a0 */
#else
0x06, 0x02, 0x00, /* j 1f */
0x00, /* .literal_position */
0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
/* 1: */
0x01, 0xfe, 0xff, /* l32r a0, entry_pc */
0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */
0xa0, 0x00, 0x00, /* jx a0 */
#endif
};
uint32_t entry_pc = tswap32(entry_point);
uint32_t entry_a2 = tswap32(tagptr);
memcpy(boot + 4, &entry_pc, sizeof(entry_pc));
memcpy(boot + 8, &entry_a2, sizeof(entry_a2));
cpu_physical_memory_write(env->pc, boot, sizeof(boot));
}
} else {
if (flash) {
MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
MemoryRegion *flash_io = g_malloc(sizeof(*flash_io));
uint32_t size = env->config->sysrom.location[0].size;
if (board->flash->size - board->flash->boot_base < size) {
size = board->flash->size - board->flash->boot_base;
}
memory_region_init_alias(flash_io, NULL, "xtfpga.flash",
flash_mr, board->flash->boot_base, size);
memory_region_add_subregion(system_memory,
env->config->sysrom.location[0].addr,
flash_io);
} else {
xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
system_memory);
}
}
}
/* Initialize the C1700 Platform */
static int c1700_init_platform(c1700_t *router)
{
vm_instance_t *vm = router->vm;
vm_obj_t *obj;
cpu_ppc_t *cpu;
cpu_gen_t *gen;
/* Copy config register setup into "active" config register */
vm->conf_reg = vm->conf_reg_setup;
/* Create Console and AUX ports */
vm_init_vtty(vm);
/* Create a CPU group */
vm->cpu_group = cpu_group_create("System CPU");
/* Initialize the virtual PowerPC processor */
if (!(gen = cpu_create(vm,CPU_TYPE_PPC32,0))) {
vm_error(vm,"unable to create CPU!\n");
return(-1);
}
cpu = CPU_PPC32(gen);
/* Add this CPU to the system CPU group */
cpu_group_add(vm->cpu_group,gen);
vm->boot_cpu = gen;
/* Set processor ID */
ppc32_set_pvr(cpu,0x00500202);
/* Mark the Network IO interrupt as high priority */
vm->irq_idle_preempt[C1700_NETIO_IRQ] = TRUE;
vm->irq_idle_preempt[C1700_DUART_IRQ] = TRUE;
/* Copy some parameters from VM to CPU (idle PC, ...) */
cpu->idle_pc = vm->idle_pc;
if (vm->timer_irq_check_itv)
cpu->timer_irq_check_itv = vm->timer_irq_check_itv;
/* Remote emulator control */
dev_remote_control_init(vm,0xf6000000,0x1000);
/* MPC860 */
cpu->mpc860_immr = C1700_MPC860_ADDR;
if (dev_mpc860_init(vm,"MPC860",C1700_MPC860_ADDR,0x10000) == -1)
return(-1);
if (!(obj = vm_object_find(router->vm,"MPC860")))
return(-1);
router->mpc_data = obj->data;
/* IO FPGA */
if (dev_c1700_iofpga_init(router,C1700_IOFPGA_ADDR,0x10000) == -1)
return(-1);
if (!(obj = vm_object_find(router->vm,"io_fpga")))
return(-1);
router->iofpga_data = obj->data;
/* Initialize the chassis */
if (c1700_init(router) == -1)
return(-1);
/* Initialize RAM */
vm_ram_init(vm,0x00000000ULL);
/* Initialize ROM */
if (!vm->rom_filename) {
/* use embedded ROM */
dev_rom_init(vm,"rom",C1700_ROM_ADDR,512*1024,
ppc32_microcode,ppc32_microcode_len);
} else {
/* use alternate ROM */
dev_ram_init(vm,"rom",TRUE,TRUE,NULL,FALSE,C1700_ROM_ADDR,512*1024);
}
/* RAM aliasing */
dev_create_ram_alias(vm,"ram_alias","ram",0x80000000,vm->ram_size*1048576);
/* NVRAM */
dev_nvram_init(vm,"nvram",
C1700_NVRAM_ADDR,vm->nvram_size*1024,&vm->conf_reg);
/* Bootflash (4 Mb) */
dev_bootflash_init(vm,"bootflash","c1700-bootflash-4mb",C1700_FLASH_ADDR);
/* Initialize the NS16552 DUART */
dev_ns16552_init(vm,C1700_DUART_ADDR,0x1000,0,C1700_DUART_IRQ,
vm->vtty_con,vm->vtty_aux);
/* Initialize Network Modules */
if (vm_slot_init_all(vm) == -1)
return(-1);
/* Show device list */
c1700_show_hardware(router);
return(0);
}
/* Initialize the adm5120 Platform (MIPS) */
static int adm5120_init_platform (adm5120_t * adm5120)
{
struct vm_instance *vm = adm5120->vm;
cpu_mips_t *cpu0;
void *(*cpu_run_fn) (void *);
vm_init_vtty (vm);
/* Create a CPU group */
vm->cpu_group = cpu_group_create ("System CPU");
/* Initialize the virtual MIPS processor */
if (!(cpu0 = cpu_create (vm, CPU_TYPE_MIPS32, 0))) {
vm_error (vm, "unable to create CPU0!\n");
return (-1);
}
/* Add this CPU to the system CPU group */
cpu_group_add (vm->cpu_group, cpu0);
vm->boot_cpu = cpu0;
cpu_run_fn = (void *) mips_exec_run_cpu;
/* create the CPU thread execution */
if (pthread_create (&cpu0->cpu_thread, NULL, cpu_run_fn, cpu0) != 0) {
fprintf (stderr, "cpu_create: unable to create thread for CPU%u\n",
0);
free (cpu0);
return (-1);
}
cpu0->addr_bus_mask = ADM5120_ADDR_BUS_MASK;
/* Initialize RAM */
vm_ram_init (vm, 0x00000000ULL);
/* Initialize ROM */
/*if (vm->rom_size!=0)
* {
* if (dev_rom_init(vm, "ROM")==-1)
* return (-1);
* } */
/* Initialize FLASH */
if ((vm->flash_size != 0) && (vm->flash_type == FLASH_TYPE_NOR_FLASH))
if (dev_nor_flash_4m_init (vm, "NORFLASH4M") == -1)
return (-1);
if (dev_sw_init (vm, "SW", ADM5120_SWCTRL_BASE, SW_INDEX_MAX * 4) == -1)
return (-1);
if (dev_mpmc_init (vm, "MPMC", ADM5120_MPMC_BASE,
MPMC_INDEX_MAX * 4) == -1)
return (-1);
if (dev_intctrl_init (vm, "INT CTRL", ADM5120_INTC_BASE,
INTCTRL_INDEX_MAX * 4) == -1)
return (-1);
if (dev_uart_init (vm, "UART 0", ADM5120_UART0_BASE, 0x24, vm->vtty_con1,
0) == -1)
return (-1);
if (dev_uart_init (vm, "UART 1", ADM5120_UART1_BASE, 0x24, vm->vtty_con2,
0) == -1)
return (-1);
if (dev_pci_init (vm, "PCI", ADM5120_PCI_BASE, PCI_INDEX_MAX * 4) == -1)
return (-1);
return (0);
}
static void mips_cps_realize(DeviceState *dev, Error **errp)
{
MIPSCPSState *s = MIPS_CPS(dev);
CPUMIPSState *env;
MIPSCPU *cpu;
int i;
Error *err = NULL;
target_ulong gcr_base;
bool itu_present = false;
bool saar_present = false;
for (i = 0; i < s->num_vp; i++) {
cpu = MIPS_CPU(cpu_create(s->cpu_type));
/* Init internal devices */
cpu_mips_irq_init_cpu(cpu);
cpu_mips_clock_init(cpu);
env = &cpu->env;
if (cpu_mips_itu_supported(env)) {
itu_present = true;
/* Attach ITC Tag to the VP */
env->itc_tag = mips_itu_get_tag_region(&s->itu);
env->itu = &s->itu;
}
qemu_register_reset(main_cpu_reset, cpu);
}
cpu = MIPS_CPU(first_cpu);
env = &cpu->env;
saar_present = (bool)env->saarp;
/* Inter-Thread Communication Unit */
if (itu_present) {
object_initialize(&s->itu, sizeof(s->itu), TYPE_MIPS_ITU);
qdev_set_parent_bus(DEVICE(&s->itu), sysbus_get_default());
object_property_set_int(OBJECT(&s->itu), 16, "num-fifo", &err);
object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores", &err);
object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-present",
&err);
if (saar_present) {
qdev_prop_set_ptr(DEVICE(&s->itu), "saar", (void *)&env->CP0_SAAR);
}
object_property_set_bool(OBJECT(&s->itu), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->container, 0,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0));
}
/* Cluster Power Controller */
object_initialize(&s->cpc, sizeof(s->cpc), TYPE_MIPS_CPC);
qdev_set_parent_bus(DEVICE(&s->cpc), sysbus_get_default());
object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp", &err);
object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running", &err);
object_property_set_bool(OBJECT(&s->cpc), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->container, 0,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0));
/* Global Interrupt Controller */
object_initialize(&s->gic, sizeof(s->gic), TYPE_MIPS_GIC);
qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
object_property_set_int(OBJECT(&s->gic), s->num_vp, "num-vp", &err);
object_property_set_int(OBJECT(&s->gic), 128, "num-irq", &err);
object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->container, 0,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0));
/* Global Configuration Registers */
gcr_base = env->CP0_CMGCRBase << 4;
object_initialize(&s->gcr, sizeof(s->gcr), TYPE_MIPS_GCR);
qdev_set_parent_bus(DEVICE(&s->gcr), sysbus_get_default());
object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp", &err);
object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev", &err);
object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base", &err);
object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->gic.mr), "gic", &err);
object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->cpc.mr), "cpc", &err);
object_property_set_bool(OBJECT(&s->gcr), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
memory_region_add_subregion(&s->container, gcr_base,
sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0));
}
/* PowerPC Mac99 hardware initialisation */
static void ppc_core99_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
const char *boot_device = machine->boot_order;
PowerPCCPU *cpu = NULL;
CPUPPCState *env = NULL;
char *filename;
qemu_irq *pic, **openpic_irqs;
MemoryRegion *isa = g_new(MemoryRegion, 1);
MemoryRegion *unin_memory = g_new(MemoryRegion, 1);
MemoryRegion *unin2_memory = g_new(MemoryRegion, 1);
int linux_boot, i, j, k;
MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1);
hwaddr kernel_base, initrd_base, cmdline_base = 0;
long kernel_size, initrd_size;
PCIBus *pci_bus;
NewWorldMacIOState *macio;
MACIOIDEState *macio_ide;
BusState *adb_bus;
MacIONVRAMState *nvr;
int bios_size, ndrv_size;
uint8_t *ndrv_file;
int ppc_boot_device;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
void *fw_cfg;
int machine_arch;
SysBusDevice *s;
DeviceState *dev, *pic_dev;
int *token = g_new(int, 1);
hwaddr nvram_addr = 0xFFF04000;
uint64_t tbfreq;
linux_boot = (kernel_filename != NULL);
/* init CPUs */
for (i = 0; i < smp_cpus; i++) {
cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
/* Set time-base frequency to 100 Mhz */
cpu_ppc_tb_init(env, TBFREQ);
qemu_register_reset(ppc_core99_reset, cpu);
}
/* allocate RAM */
memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size);
memory_region_add_subregion(get_system_memory(), 0, ram);
/* allocate and load BIOS */
memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE,
&error_fatal);
if (bios_name == NULL)
bios_name = PROM_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
memory_region_set_readonly(bios, true);
memory_region_add_subregion(get_system_memory(), PROM_ADDR, bios);
/* Load OpenBIOS (ELF) */
if (filename) {
bios_size = load_elf(filename, NULL, NULL, NULL,
NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
g_free(filename);
} else {
bios_size = -1;
}
if (bios_size < 0 || bios_size > BIOS_SIZE) {
error_report("could not load PowerPC bios '%s'", bios_name);
exit(1);
}
if (linux_boot) {
uint64_t lowaddr = 0;
int bswap_needed;
#ifdef BSWAP_NEEDED
bswap_needed = 1;
#else
bswap_needed = 0;
#endif
kernel_base = KERNEL_LOAD_ADDR;
kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
0, 0);
if (kernel_size < 0)
kernel_size = load_aout(kernel_filename, kernel_base,
ram_size - kernel_base, bswap_needed,
TARGET_PAGE_SIZE);
if (kernel_size < 0)
kernel_size = load_image_targphys(kernel_filename,
kernel_base,
ram_size - kernel_base);
if (kernel_size < 0) {
error_report("could not load kernel '%s'", kernel_filename);
exit(1);
}
/* load initrd */
if (initrd_filename) {
initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
initrd_size = load_image_targphys(initrd_filename, initrd_base,
ram_size - initrd_base);
if (initrd_size < 0) {
error_report("could not load initial ram disk '%s'",
initrd_filename);
exit(1);
}
cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
} else {
initrd_base = 0;
initrd_size = 0;
cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
}
ppc_boot_device = 'm';
} else {
kernel_base = 0;
kernel_size = 0;
initrd_base = 0;
initrd_size = 0;
ppc_boot_device = '\0';
/* We consider that NewWorld PowerMac never have any floppy drive
* For now, OHW cannot boot from the network.
*/
for (i = 0; boot_device[i] != '\0'; i++) {
if (boot_device[i] >= 'c' && boot_device[i] <= 'f') {
ppc_boot_device = boot_device[i];
break;
}
}
if (ppc_boot_device == '\0') {
error_report("No valid boot device for Mac99 machine");
exit(1);
}
}
/* Register 8 MB of ISA IO space */
memory_region_init_alias(isa, NULL, "isa_mmio",
get_system_io(), 0, 0x00800000);
memory_region_add_subregion(get_system_memory(), 0xf2000000, isa);
/* UniN init: XXX should be a real device */
memory_region_init_io(unin_memory, NULL, &unin_ops, token, "unin", 0x1000);
memory_region_add_subregion(get_system_memory(), 0xf8000000, unin_memory);
memory_region_init_io(unin2_memory, NULL, &unin_ops, token, "unin", 0x1000);
memory_region_add_subregion(get_system_memory(), 0xf3000000, unin2_memory);
openpic_irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
openpic_irqs[0] =
g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
for (i = 0; i < smp_cpus; i++) {
/* Mac99 IRQ connection between OpenPIC outputs pins
* and PowerPC input pins
*/
switch (PPC_INPUT(env)) {
case PPC_FLAGS_INPUT_6xx:
openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
openpic_irqs[i][OPENPIC_OUTPUT_INT] =
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
/* Not connected ? */
openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
/* Check this */
openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
break;
#if defined(TARGET_PPC64)
case PPC_FLAGS_INPUT_970:
openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
openpic_irqs[i][OPENPIC_OUTPUT_INT] =
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
/* Not connected ? */
openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
/* Check this */
openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
break;
#endif /* defined(TARGET_PPC64) */
default:
error_report("Bus model not supported on mac99 machine");
exit(1);
}
}
pic = g_new0(qemu_irq, 64);
pic_dev = qdev_create(NULL, TYPE_OPENPIC);
qdev_prop_set_uint32(pic_dev, "model", OPENPIC_MODEL_KEYLARGO);
qdev_init_nofail(pic_dev);
s = SYS_BUS_DEVICE(pic_dev);
k = 0;
for (i = 0; i < smp_cpus; i++) {
for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
sysbus_connect_irq(s, k++, openpic_irqs[i][j]);
}
}
for (i = 0; i < 64; i++) {
pic[i] = qdev_get_gpio_in(pic_dev, i);
}
if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
/* 970 gets a U3 bus */
pci_bus = pci_pmac_u3_init(pic, get_system_memory(), get_system_io());
machine_arch = ARCH_MAC99_U3;
} else {
pci_bus = pci_pmac_init(pic, get_system_memory(), get_system_io());
machine_arch = ARCH_MAC99;
}
object_property_set_bool(OBJECT(pci_bus), true, "realized", &error_abort);
machine->usb |= defaults_enabled() && !machine->usb_disabled;
/* Timebase Frequency */
if (kvm_enabled()) {
tbfreq = kvmppc_get_tbfreq();
} else {
tbfreq = TBFREQ;
}
/* MacIO */
macio = NEWWORLD_MACIO(pci_create(pci_bus, -1, TYPE_NEWWORLD_MACIO));
dev = DEVICE(macio);
qdev_connect_gpio_out(dev, 0, pic[0x19]); /* CUDA */
qdev_connect_gpio_out(dev, 1, pic[0x24]); /* ESCC-B */
qdev_connect_gpio_out(dev, 2, pic[0x25]); /* ESCC-A */
qdev_connect_gpio_out(dev, 3, pic[0x0d]); /* IDE */
qdev_connect_gpio_out(dev, 4, pic[0x02]); /* IDE DMA */
qdev_connect_gpio_out(dev, 5, pic[0x0e]); /* IDE */
qdev_connect_gpio_out(dev, 6, pic[0x03]); /* IDE DMA */
qdev_prop_set_uint64(dev, "frequency", tbfreq);
object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic",
&error_abort);
qdev_init_nofail(dev);
/* We only emulate 2 out of 3 IDE controllers for now */
ide_drive_get(hd, ARRAY_SIZE(hd));
macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
"ide[0]"));
macio_ide_init_drives(macio_ide, hd);
macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
"ide[1]"));
macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
adb_bus = qdev_get_child_bus(dev, "adb.0");
dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
qdev_init_nofail(dev);
dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
qdev_init_nofail(dev);
if (machine->usb) {
pci_create_simple(pci_bus, -1, "pci-ohci");
/* U3 needs to use USB for input because Linux doesn't support via-cuda
on PPC64 */
if (machine_arch == ARCH_MAC99_U3) {
USBBus *usb_bus = usb_bus_find(-1);
usb_create_simple(usb_bus, "usb-kbd");
usb_create_simple(usb_bus, "usb-mouse");
}
}
pci_vga_init(pci_bus);
if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) {
graphic_depth = 15;
}
for (i = 0; i < nb_nics; i++) {
pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
}
/* The NewWorld NVRAM is not located in the MacIO device */
#ifdef CONFIG_KVM
if (kvm_enabled() && getpagesize() > 4096) {
/* We can't combine read-write and read-only in a single page, so
move the NVRAM out of ROM again for KVM */
nvram_addr = 0xFFE00000;
}
#endif
dev = qdev_create(NULL, TYPE_MACIO_NVRAM);
qdev_prop_set_uint32(dev, "size", 0x2000);
qdev_prop_set_uint32(dev, "it_shift", 1);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr);
nvr = MACIO_NVRAM(dev);
pmac_format_nvram_partition(nvr, 0x2000);
/* No PCI init: the BIOS will do it */
fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
}
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
if (kvm_enabled()) {
#ifdef CONFIG_KVM
uint8_t *hypercall;
hypercall = g_malloc(16);
kvmppc_get_hypercall(env, hypercall, 16);
fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
#endif
}
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
/* Mac OS X requires a "known good" clock-frequency value; pass it one. */
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr);
/* MacOS NDRV VGA driver */
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME);
if (filename) {
ndrv_size = get_image_size(filename);
if (ndrv_size != -1) {
ndrv_file = g_malloc(ndrv_size);
ndrv_size = load_image(filename, ndrv_file);
fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size);
}
g_free(filename);
}
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
/* Initialize the PPC32 VM test Platform */
static int ppc32_vmtest_init_platform(vm_instance_t *vm)
{
_maybe_used cpu_ppc_t *cpu0;
cpu_gen_t *gen0;
/* Create Console and AUX ports */
vm_init_vtty(vm);
/* Create a CPU group */
vm->cpu_group = cpu_group_create("System CPU");
/* Initialize the virtual PowerPC processor */
if (!(gen0 = cpu_create(vm,CPU_TYPE_PPC32,0))) {
vm_error(vm,"unable to create CPU0!\n");
return(-1);
}
cpu0 = CPU_PPC32(gen0);
/* Enable as PowerPC 405 */
//ppc32_set_pvr(cpu0,PPC32_PVR_405 | 0x0102);
/* Add this CPU to the system CPU group */
cpu_group_add(vm->cpu_group,gen0);
vm->boot_cpu = gen0;
/* Set IRQ vectors */
vm->set_irq = ppc32_vmtest_set_irq;
vm->clear_irq = ppc32_vmtest_clear_irq;
#if 0
{
vm_obj_t *obj;
/* Initialize ROM (as a Flash) */
if (!(obj = dev_flash_init(vm,"rom",0xFF000000,16*1048576)))
return(-1);
dev_flash_copy_data(obj,0x0F00000,ppc32_microcode,ppc32_microcode_len);
}
#endif
//dev_bootflash_init(vm,"bootflash",0xFF000000,8*1048576);
#if 1
/* Initialize ROM */
if (!vm->rom_filename) {
/* use embedded ROM */
dev_rom_init(vm,"rom",0xFFF00000,512*1024,
ppc32_microcode,ppc32_microcode_len);
} else {
/* use alternate ROM */
dev_ram_init(vm,"rom",TRUE,TRUE,NULL,FALSE,
0xFFF00000,512*1024);
}
#endif
/* Remote emulator control */
dev_remote_control_init(vm,0xf6000000,0x1000);
/* Initialize RAM */
vm_ram_init(vm,0x00000000);
/* RAM aliasing */
dev_create_ram_alias(vm,"ram_alias","ram",0x80000000,vm->ram_size*1048576);
/* Display the device list */
dev_show_list(vm);
return(0);
}
psim_create(const char *file_name,
device *root)
{
int cpu_nr;
const char *env;
psim *system;
os_emul *os_emulation;
int nr_cpus;
/* given this partially populated device tree, os_emul_create() uses
it and file_name to determine the selected emulation and hence
further populate the tree with any other required nodes. */
os_emulation = os_emul_create(file_name, root);
if (os_emulation == NULL)
error("psim: either file %s was not reconized or unreconized or unknown os-emulation type\n", file_name);
/* fill in the missing real number of CPU's */
nr_cpus = tree_find_integer_property(root, "/openprom/options/smp");
if (MAX_NR_PROCESSORS < nr_cpus)
error("target and configured number of cpus conflict\n");
/* fill in the missing TARGET BYTE ORDER information */
current_target_byte_order
= (tree_find_boolean_property(root, "/options/little-endian?")
? LITTLE_ENDIAN
: BIG_ENDIAN);
if (CURRENT_TARGET_BYTE_ORDER != current_target_byte_order)
error("target and configured byte order conflict\n");
/* fill in the missing HOST BYTE ORDER information */
current_host_byte_order = (current_host_byte_order = 1,
(*(char*)(¤t_host_byte_order)
? LITTLE_ENDIAN
: BIG_ENDIAN));
if (CURRENT_HOST_BYTE_ORDER != current_host_byte_order)
error("host and configured byte order conflict\n");
/* fill in the missing OEA/VEA information */
env = tree_find_string_property(root, "/openprom/options/env");
current_environment = ((strcmp(env, "user") == 0
|| strcmp(env, "uea") == 0)
? USER_ENVIRONMENT
: (strcmp(env, "virtual") == 0
|| strcmp(env, "vea") == 0)
? VIRTUAL_ENVIRONMENT
: (strcmp(env, "operating") == 0
|| strcmp(env, "oea") == 0)
? OPERATING_ENVIRONMENT
: 0);
if (current_environment == 0)
error("unreconized /options env property\n");
if (CURRENT_ENVIRONMENT != current_environment)
error("target and configured environment conflict\n");
/* fill in the missing ALLIGNMENT information */
current_alignment
= (tree_find_boolean_property(root, "/openprom/options/strict-alignment?")
? STRICT_ALIGNMENT
: NONSTRICT_ALIGNMENT);
if (CURRENT_ALIGNMENT != current_alignment)
error("target and configured alignment conflict\n");
/* fill in the missing FLOATING POINT information */
current_floating_point
= (tree_find_boolean_property(root, "/openprom/options/floating-point?")
? HARD_FLOATING_POINT
: SOFT_FLOATING_POINT);
if (CURRENT_FLOATING_POINT != current_floating_point)
error("target and configured floating-point conflict\n");
/* fill in the missing STDIO information */
current_stdio
= (tree_find_boolean_property(root, "/openprom/options/use-stdio?")
? DO_USE_STDIO
: DONT_USE_STDIO);
if (CURRENT_STDIO != current_stdio)
error("target and configured stdio interface conflict\n");
/* sort out the level of detail for issue modeling */
current_model_issue
= tree_find_integer_property(root, "/openprom/options/model-issue");
if (CURRENT_MODEL_ISSUE != current_model_issue)
error("target and configured model-issue conflict\n");
/* sort out our model architecture - wrong.
FIXME: this should be obtaining the required information from the
device tree via the "/chosen" property "cpu" which is an instance
(ihandle) for the only executing processor. By converting that
ihandle into the corresponding cpu's phandle and then querying
the "name" property, the cpu type can be determined. Ok? */
model_set(tree_find_string_property(root, "/openprom/options/model"));
/* create things */
system = ZALLOC(psim);
system->events = event_queue_create();
system->memory = core_from_device(root);
system->monitor = mon_create();
system->nr_cpus = nr_cpus;
system->os_emulation = os_emulation;
system->devices = root;
/* now all the processors attaching to each their per-cpu information */
for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++) {
system->processors[cpu_nr] = cpu_create(system,
system->memory,
mon_cpu(system->monitor,
cpu_nr),
system->os_emulation,
cpu_nr);
}
/* dump out the contents of the device tree */
if (ppc_trace[trace_print_device_tree] || ppc_trace[trace_dump_device_tree])
tree_print(root);
if (ppc_trace[trace_dump_device_tree])
error("");
return system;
}
static void
milkymist_init(MachineState *machine)
{
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
LM32CPU *cpu;
CPULM32State *env;
int kernel_size;
DriveInfo *dinfo;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *phys_sdram = g_new(MemoryRegion, 1);
qemu_irq irq[32];
int i;
char *bios_filename;
ResetInfo *reset_info;
/* memory map */
hwaddr flash_base = 0x00000000;
size_t flash_sector_size = 128 * KiB;
size_t flash_size = 32 * MiB;
hwaddr sdram_base = 0x40000000;
size_t sdram_size = 128 * MiB;
hwaddr initrd_base = sdram_base + 0x1002000;
hwaddr cmdline_base = sdram_base + 0x1000000;
size_t initrd_max = sdram_size - 0x1002000;
reset_info = g_malloc0(sizeof(ResetInfo));
cpu = LM32_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
reset_info->cpu = cpu;
cpu_lm32_set_phys_msb_ignore(env, 1);
memory_region_allocate_system_memory(phys_sdram, NULL, "milkymist.sdram",
sdram_size);
memory_region_add_subregion(address_space_mem, sdram_base, phys_sdram);
dinfo = drive_get(IF_PFLASH, 0, 0);
/* Numonyx JS28F256J3F105 */
pflash_cfi01_register(flash_base, "milkymist.flash", flash_size,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
flash_sector_size, 2, 0x00, 0x89, 0x00, 0x1d, 1);
/* create irq lines */
env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0));
for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in(env->pic_state, i);
}
/* load bios rom */
if (bios_name == NULL) {
bios_name = BIOS_FILENAME;
}
bios_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (bios_filename) {
if (load_image_targphys(bios_filename, BIOS_OFFSET, BIOS_SIZE) < 0) {
error_report("could not load bios '%s'", bios_filename);
exit(1);
}
}
reset_info->bootstrap_pc = BIOS_OFFSET;
/* if no kernel is given no valid bios rom is a fatal error */
if (!kernel_filename && !dinfo && !bios_filename && !qtest_enabled()) {
error_report("could not load Milkymist One bios '%s'", bios_name);
exit(1);
}
g_free(bios_filename);
milkymist_uart_create(0x60000000, irq[0], serial_hd(0));
milkymist_sysctl_create(0x60001000, irq[1], irq[2], irq[3],
80000000, 0x10014d31, 0x0000041f, 0x00000001);
milkymist_hpdmc_create(0x60002000);
milkymist_vgafb_create(0x60003000, 0x40000000, 0x0fffffff);
milkymist_memcard_create(0x60004000);
milkymist_ac97_create(0x60005000, irq[4], irq[5], irq[6], irq[7]);
milkymist_pfpu_create(0x60006000, irq[8]);
if (machine->enable_graphics) {
milkymist_tmu2_create(0x60007000, irq[9]);
}
milkymist_minimac2_create(0x60008000, 0x30000000, irq[10], irq[11]);
milkymist_softusb_create(0x6000f000, irq[15],
0x20000000, 0x1000, 0x20020000, 0x2000);
/* make sure juart isn't the first chardev */
env->juart_state = lm32_juart_init(serial_hd(1));
if (kernel_filename) {
uint64_t entry;
/* Boots a kernel elf binary. */
kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
&entry, NULL, NULL,
1, EM_LATTICEMICO32, 0, 0);
reset_info->bootstrap_pc = entry;
if (kernel_size < 0) {
kernel_size = load_image_targphys(kernel_filename, sdram_base,
sdram_size);
reset_info->bootstrap_pc = sdram_base;
}
if (kernel_size < 0) {
error_report("could not load kernel '%s'", kernel_filename);
exit(1);
}
}
if (kernel_cmdline && strlen(kernel_cmdline)) {
pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
kernel_cmdline);
reset_info->cmdline_base = (uint32_t)cmdline_base;
}
if (initrd_filename) {
size_t initrd_size;
initrd_size = load_image_targphys(initrd_filename, initrd_base,
initrd_max);
reset_info->initrd_base = (uint32_t)initrd_base;
reset_info->initrd_size = (uint32_t)initrd_size;
}
qemu_register_reset(main_cpu_reset, reset_info);
}
static void bamboo_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *isa = g_new(MemoryRegion, 1);
MemoryRegion *ram_memories
= g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories));
hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS];
hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS];
qemu_irq *pic;
qemu_irq *irqs;
PCIBus *pcibus;
PowerPCCPU *cpu;
CPUPPCState *env;
uint64_t elf_entry;
uint64_t elf_lowaddr;
hwaddr loadaddr = 0;
target_long initrd_size = 0;
DeviceState *dev;
int success;
int i;
cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
if (env->mmu_model != POWERPC_MMU_BOOKE) {
fprintf(stderr, "MMU model %i not supported by this machine.\n",
env->mmu_model);
exit(1);
}
qemu_register_reset(main_cpu_reset, cpu);
ppc_booke_timers_init(cpu, 400000000, 0);
ppc_dcr_init(env, NULL, NULL);
/* interrupt controller */
irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
/* SDRAM controller */
memset(ram_bases, 0, sizeof(ram_bases));
memset(ram_sizes, 0, sizeof(ram_sizes));
ram_size = ppc4xx_sdram_adjust(ram_size, PPC440EP_SDRAM_NR_BANKS,
ram_memories,
ram_bases, ram_sizes,
ppc440ep_sdram_bank_sizes);
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories,
ram_bases, ram_sizes, 1);
/* PCI */
dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
PPC440EP_PCI_CONFIG,
pic[pci_irq_nrs[0]], pic[pci_irq_nrs[1]],
pic[pci_irq_nrs[2]], pic[pci_irq_nrs[3]],
NULL);
pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
if (!pcibus) {
fprintf(stderr, "couldn't create PCI controller!\n");
exit(1);
}
memory_region_init_alias(isa, NULL, "isa_mmio",
get_system_io(), 0, PPC440EP_PCI_IOLEN);
memory_region_add_subregion(get_system_memory(), PPC440EP_PCI_IO, isa);
if (serial_hds[0] != NULL) {
serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
DEVICE_BIG_ENDIAN);
}
if (serial_hds[1] != NULL) {
serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
DEVICE_BIG_ENDIAN);
}
if (pcibus) {
/* Register network interfaces. */
for (i = 0; i < nb_nics; i++) {
/* There are no PCI NICs on the Bamboo board, but there are
* PCI slots, so we can pick whatever default model we want. */
pci_nic_init_nofail(&nd_table[i], pcibus, "e1000", NULL);
}
}
/* Load kernel. */
if (kernel_filename) {
success = load_uimage(kernel_filename, &entry, &loadaddr, NULL,
NULL, NULL);
if (success < 0) {
success = load_elf(kernel_filename, NULL, NULL, &elf_entry,
&elf_lowaddr, NULL, 1, PPC_ELF_MACHINE,
0, 0);
entry = elf_entry;
loadaddr = elf_lowaddr;
}
/* XXX try again as binary */
if (success < 0) {
fprintf(stderr, "qemu: could not load kernel '%s'\n",
kernel_filename);
exit(1);
}
}
/* Load initrd. */
if (initrd_filename) {
initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR,
ram_size - RAMDISK_ADDR);
if (initrd_size < 0) {
fprintf(stderr, "qemu: could not load ram disk '%s' at %x\n",
initrd_filename, RAMDISK_ADDR);
exit(1);
}
}
/* If we're loading a kernel directly, we must load the device tree too. */
if (kernel_filename) {
if (bamboo_load_device_tree(FDT_ADDR, ram_size, RAMDISK_ADDR,
initrd_size, kernel_cmdline) < 0) {
fprintf(stderr, "couldn't load device tree\n");
exit(1);
}
}
}
static void ppc_heathrow_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
const char *boot_device = machine->boot_order;
MemoryRegion *sysmem = get_system_memory();
PowerPCCPU *cpu = NULL;
CPUPPCState *env = NULL;
char *filename;
int linux_boot, i;
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
uint32_t kernel_base, initrd_base, cmdline_base = 0;
int32_t kernel_size, initrd_size;
PCIBus *pci_bus;
OldWorldMacIOState *macio;
MACIOIDEState *macio_ide;
SysBusDevice *s;
DeviceState *dev, *pic_dev;
BusState *adb_bus;
int bios_size;
uint16_t ppc_boot_device;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
void *fw_cfg;
uint64_t tbfreq;
linux_boot = (kernel_filename != NULL);
/* init CPUs */
for (i = 0; i < smp_cpus; i++) {
cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
/* Set time-base frequency to 16.6 Mhz */
cpu_ppc_tb_init(env, TBFREQ);
qemu_register_reset(ppc_heathrow_reset, cpu);
}
/* allocate RAM */
if (ram_size > 2047 * MiB) {
error_report("Too much memory for this machine: %" PRId64 " MB, "
"maximum 2047 MB", ram_size / MiB);
exit(1);
}
memory_region_allocate_system_memory(ram, NULL, "ppc_heathrow.ram",
ram_size);
memory_region_add_subregion(sysmem, 0, ram);
/* allocate and load BIOS */
memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE,
&error_fatal);
if (bios_name == NULL)
bios_name = PROM_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
memory_region_set_readonly(bios, true);
memory_region_add_subregion(sysmem, PROM_ADDR, bios);
/* Load OpenBIOS (ELF) */
if (filename) {
bios_size = load_elf(filename, NULL, 0, NULL, NULL, NULL, NULL,
1, PPC_ELF_MACHINE, 0, 0);
g_free(filename);
} else {
bios_size = -1;
}
if (bios_size < 0 || bios_size > BIOS_SIZE) {
error_report("could not load PowerPC bios '%s'", bios_name);
exit(1);
}
if (linux_boot) {
uint64_t lowaddr = 0;
int bswap_needed;
#ifdef BSWAP_NEEDED
bswap_needed = 1;
#else
bswap_needed = 0;
#endif
kernel_base = KERNEL_LOAD_ADDR;
kernel_size = load_elf(kernel_filename, NULL,
translate_kernel_address, NULL,
NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
0, 0);
if (kernel_size < 0)
kernel_size = load_aout(kernel_filename, kernel_base,
ram_size - kernel_base, bswap_needed,
TARGET_PAGE_SIZE);
if (kernel_size < 0)
kernel_size = load_image_targphys(kernel_filename,
kernel_base,
ram_size - kernel_base);
if (kernel_size < 0) {
error_report("could not load kernel '%s'", kernel_filename);
exit(1);
}
/* load initrd */
if (initrd_filename) {
initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
initrd_size = load_image_targphys(initrd_filename, initrd_base,
ram_size - initrd_base);
if (initrd_size < 0) {
error_report("could not load initial ram disk '%s'",
initrd_filename);
exit(1);
}
cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
} else {
initrd_base = 0;
initrd_size = 0;
cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
}
ppc_boot_device = 'm';
} else {
kernel_base = 0;
kernel_size = 0;
initrd_base = 0;
initrd_size = 0;
ppc_boot_device = '\0';
for (i = 0; boot_device[i] != '\0'; i++) {
/* TOFIX: for now, the second IDE channel is not properly
* used by OHW. The Mac floppy disk are not emulated.
* For now, OHW cannot boot from the network.
*/
#if 0
if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
ppc_boot_device = boot_device[i];
break;
}
#else
if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
ppc_boot_device = boot_device[i];
break;
}
#endif
}
if (ppc_boot_device == '\0') {
error_report("No valid boot device for G3 Beige machine");
exit(1);
}
}
/* XXX: we register only 1 output pin for heathrow PIC */
pic_dev = qdev_create(NULL, TYPE_HEATHROW);
qdev_init_nofail(pic_dev);
/* Connect the heathrow PIC outputs to the 6xx bus */
for (i = 0; i < smp_cpus; i++) {
switch (PPC_INPUT(env)) {
case PPC_FLAGS_INPUT_6xx:
qdev_connect_gpio_out(pic_dev, 0,
((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]);
break;
default:
error_report("Bus model not supported on OldWorld Mac machine");
exit(1);
}
}
/* Timebase Frequency */
if (kvm_enabled()) {
tbfreq = kvmppc_get_tbfreq();
} else {
tbfreq = TBFREQ;
}
/* init basic PC hardware */
if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
error_report("Only 6xx bus is supported on heathrow machine");
exit(1);
}
/* Grackle PCI host bridge */
dev = qdev_create(NULL, TYPE_GRACKLE_PCI_HOST_BRIDGE);
qdev_prop_set_uint32(dev, "ofw-addr", 0x80000000);
object_property_set_link(OBJECT(dev), OBJECT(pic_dev), "pic",
&error_abort);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, GRACKLE_BASE);
sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000);
/* PCI hole */
memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
sysbus_mmio_get_region(s, 2));
/* Register 2 MB of ISA IO space */
memory_region_add_subregion(get_system_memory(), 0xfe000000,
sysbus_mmio_get_region(s, 3));
pci_bus = PCI_HOST_BRIDGE(dev)->bus;
pci_vga_init(pci_bus);
for (i = 0; i < nb_nics; i++) {
pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
}
ide_drive_get(hd, ARRAY_SIZE(hd));
/* MacIO */
macio = OLDWORLD_MACIO(pci_create(pci_bus, -1, TYPE_OLDWORLD_MACIO));
dev = DEVICE(macio);
qdev_prop_set_uint64(dev, "frequency", tbfreq);
object_property_set_link(OBJECT(macio), OBJECT(pic_dev), "pic",
&error_abort);
qdev_init_nofail(dev);
macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
"ide[0]"));
macio_ide_init_drives(macio_ide, hd);
macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
"ide[1]"));
macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
adb_bus = qdev_get_child_bus(dev, "adb.0");
dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
qdev_init_nofail(dev);
dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
qdev_init_nofail(dev);
if (machine_usb(machine)) {
pci_create_simple(pci_bus, -1, "pci-ohci");
}
if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
graphic_depth = 15;
/* No PCI init: the BIOS will do it */
dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
fw_cfg = FW_CFG(dev);
qdev_prop_set_uint32(dev, "data_width", 1);
qdev_prop_set_bit(dev, "dma_enabled", false);
object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
OBJECT(fw_cfg), NULL);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, CFG_ADDR);
sysbus_mmio_map(s, 1, CFG_ADDR + 2);
fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
if (kernel_cmdline) {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
} else {
fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
}
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
if (kvm_enabled()) {
#ifdef CONFIG_KVM
uint8_t *hypercall;
hypercall = g_malloc(16);
kvmppc_get_hypercall(env, hypercall, 16);
fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
#endif
}
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
/* Mac OS X requires a "known good" clock-frequency value; pass it one. */
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
/* MacOS NDRV VGA driver */
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME);
if (filename) {
gchar *ndrv_file;
gsize ndrv_size;
if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) {
fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size);
}
g_free(filename);
}
qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
}
