int __init omap1_mcbsp_init(void) { if (cpu_is_omap730()) omap_mcbsp_count = OMAP730_MCBSP_PDATA_SZ; if (cpu_is_omap15xx()) omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ; if (cpu_is_omap16xx()) omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ; mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), GFP_KERNEL); if (!mcbsp_ptr) return -ENOMEM; if (cpu_is_omap730()) omap_mcbsp_register_board_cfg(omap730_mcbsp_pdata, OMAP730_MCBSP_PDATA_SZ); if (cpu_is_omap15xx()) omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata, OMAP15XX_MCBSP_PDATA_SZ); if (cpu_is_omap16xx()) omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata, OMAP16XX_MCBSP_PDATA_SZ); return omap_mcbsp_init(); }
int __init omap1_mcbsp_init(void) { int i; for (i = 0; i < omap_mcbsp_clks_size; i++) { if (cpu_is_omap15xx() || cpu_is_omap16xx()) { omap_mcbsp_clk_init(&omap_mcbsp_clks[i]); clk_register(&omap_mcbsp_clks[i].clk); } } if (cpu_is_omap730()) omap_mcbsp_register_board_cfg(omap730_mcbsp_pdata, OMAP730_MCBSP_PDATA_SZ); if (cpu_is_omap15xx()) omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata, OMAP15XX_MCBSP_PDATA_SZ); if (cpu_is_omap16xx()) omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata, OMAP16XX_MCBSP_PDATA_SZ); return omap_mcbsp_init(); }
void __init omap_usb_init(struct omap_usb_config *pdata) { if (cpu_is_omap730() || cpu_is_omap16xx() || cpu_is_omap24xx()) omap_otg_init(pdata); else if (cpu_is_omap15xx()) omap_1510_usb_init(pdata); else printk(KERN_ERR "USB: No init for your chip yet\n"); }
static inline int omap_32k_timer_usable(void) { int res = false; if (cpu_is_omap730() || cpu_is_omap15xx()) return res; #ifdef CONFIG_OMAP_32K_TIMER res = omap_32k_timer_init(); #endif return res; }
int __init omap1_mcbsp_init(void) { int i; for (i = 0; i < omap_mcbsp_clks_size; i++) { if (cpu_is_omap15xx() || cpu_is_omap16xx()) { omap_mcbsp_clk_init(&omap_mcbsp_clks[i]); clk_register(&omap_mcbsp_clks[i].clk); } } if (cpu_is_omap730()) omap_mcbsp_count = OMAP730_MCBSP_PDATA_SZ; if (cpu_is_omap15xx()) omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ; if (cpu_is_omap16xx()) omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ; mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), GFP_KERNEL); if (!mcbsp_ptr) return -ENOMEM; if (cpu_is_omap730()) omap_mcbsp_register_board_cfg(omap730_mcbsp_pdata, OMAP730_MCBSP_PDATA_SZ); if (cpu_is_omap15xx()) omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata, OMAP15XX_MCBSP_PDATA_SZ); if (cpu_is_omap16xx()) omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata, OMAP16XX_MCBSP_PDATA_SZ); return omap_mcbsp_init(); }
int __init omap1_mux_init(void) { if (cpu_is_omap730()) { arch_mux_cfg.pins = omap730_pins; arch_mux_cfg.size = OMAP730_PINS_SZ; arch_mux_cfg.cfg_reg = omap1_cfg_reg; } if (cpu_is_omap15xx() || cpu_is_omap16xx()) { arch_mux_cfg.pins = omap1xxx_pins; arch_mux_cfg.size = OMAP1XXX_PINS_SZ; arch_mux_cfg.cfg_reg = omap1_cfg_reg; } return omap_mux_register(&arch_mux_cfg); }
/* * Maps common IO regions for omap1. This should only get called from * board specific init. */ void __init omap1_map_common_io(void) { iotable_init(omap_io_desc, ARRAY_SIZE(omap_io_desc)); /* Normally devicemaps_init() would flush caches and tlb after * mdesc->map_io(), but we must also do it here because of the CPU * revision check below. */ local_flush_tlb_all(); flush_cache_all(); /* We want to check CPU revision early for cpu_is_omapxxxx() macros. * IO space mapping must be initialized before we can do that. */ omap_check_revision(); #ifdef CONFIG_ARCH_OMAP730 if (cpu_is_omap730()) { iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc)); } #endif #ifdef CONFIG_ARCH_OMAP850 if (cpu_is_omap850()) { iotable_init(omap850_io_desc, ARRAY_SIZE(omap850_io_desc)); } #endif #ifdef CONFIG_ARCH_OMAP15XX if (cpu_is_omap15xx()) { iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc)); } #endif #if defined(CONFIG_ARCH_OMAP16XX) if (cpu_is_omap16xx()) { iotable_init(omap16xx_io_desc, ARRAY_SIZE(omap16xx_io_desc)); } #endif omap_sram_init(); omapfb_reserve_sdram(); }
/* * The amount of SRAM depends on the core type: * 730 = 200K, 1510 = 512K, 5912 = 256K, 1610 = 16K, 1710 = 16K * Note that we cannot try to test for SRAM here because writes * to secure SRAM will hang the system. Also the SRAM is not * yet mapped at this point. */ void __init omap_detect_sram(void) { omap_sram_base = OMAP1_SRAM_BASE; if (cpu_is_omap730()) omap_sram_size = 0x32000; else if (cpu_is_omap1510()) omap_sram_size = 0x80000; else if (cpu_is_omap1610() || cpu_is_omap1621() || cpu_is_omap1710()) omap_sram_size = 0x4000; else if (cpu_is_omap1611()) omap_sram_size = 0x3e800; else { printk(KERN_ERR "Could not detect SRAM size\n"); omap_sram_size = 0x4000; } printk(KERN_INFO "SRAM size: 0x%lx\n", omap_sram_size); omap_sram_ceil = omap_sram_base + omap_sram_size; }
static void __init _omap_map_io(void) { initialized = 1; /* We have to initialize the IO space mapping before we can run * cpu_is_omapxxx() macros. */ iotable_init(omap_io_desc, ARRAY_SIZE(omap_io_desc)); omap_check_revision(); #ifdef CONFIG_ARCH_OMAP730 if (cpu_is_omap730()) { iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc)); } #endif #ifdef CONFIG_ARCH_OMAP1510 if (cpu_is_omap1510()) { iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc)); } #endif #if defined(CONFIG_ARCH_OMAP16XX) if (cpu_is_omap1610() || cpu_is_omap1710()) { iotable_init(omap1610_io_desc, ARRAY_SIZE(omap1610_io_desc)); } if (cpu_is_omap5912()) { iotable_init(omap5912_io_desc, ARRAY_SIZE(omap5912_io_desc)); } #endif /* REVISIT: Refer to OMAP5910 Errata, Advisory SYS_1: "Timeout Abort * on a Posted Write in the TIPB Bridge". */ omap_writew(0x0, MPU_PUBLIC_TIPB_CNTL); omap_writew(0x0, MPU_PRIVATE_TIPB_CNTL); /* Must init clocks early to assure that timer interrupt works */ clk_init(); }
static int __init omap_usb_init(void) { const struct omap_usb_config *config; config = omap_get_config(OMAP_TAG_USB, struct omap_usb_config); if (config == NULL) { printk(KERN_ERR "USB: No board-specific " "platform config found\n"); return -ENODEV; } platform_data = *config; if (cpu_is_omap730() || cpu_is_omap16xx() || cpu_is_omap24xx()) omap_otg_init(&platform_data); else if (cpu_is_omap15xx()) omap_1510_usb_init(&platform_data); else { printk(KERN_ERR "USB: No init for your chip yet\n"); return -ENODEV; } return 0; }
static int omap1_mcbsp_check(unsigned int id) { /* REVISIT: Check correctly for number of registered McBSPs */ if (cpu_is_omap730()) { if (id > OMAP_MAX_MCBSP_COUNT - 2) { printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1); return -ENODEV; } return 0; } if (cpu_is_omap15xx() || cpu_is_omap16xx()) { if (id > OMAP_MAX_MCBSP_COUNT - 1) { printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1); return -ENODEV; } return 0; } return -ENODEV; }
void __init omap_otg_init(struct omap_usb_config *config) { u32 syscon; int status; int alt_pingroup = 0; /* NOTE: no bus or clock setup (yet?) */ syscon = omap_readl(OTG_SYSCON_1) & 0xffff; if (!(syscon & OTG_RESET_DONE)) pr_debug("USB resets not complete?\n"); //omap_writew(0, OTG_IRQ_EN); /* pin muxing and transceiver pinouts */ if (config->pins[0] > 2) /* alt pingroup 2 */ alt_pingroup = 1; syscon |= omap_usb0_init(config->pins[0], is_usb0_device(config)); syscon |= omap_usb1_init(config->pins[1]); syscon |= omap_usb2_init(config->pins[2], alt_pingroup); pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); omap_writel(syscon, OTG_SYSCON_1); syscon = config->hmc_mode; syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */; #ifdef CONFIG_USB_OTG if (config->otg) syscon |= OTG_EN; #endif if (cpu_class_is_omap1()) pr_debug("USB_TRANSCEIVER_CTRL = %03x\n", omap_readl(USB_TRANSCEIVER_CTRL)); pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2)); omap_writel(syscon, OTG_SYSCON_2); printk("USB: hmc %d", config->hmc_mode); if (!alt_pingroup) printk(", usb2 alt %d wires", config->pins[2]); else if (config->pins[0]) printk(", usb0 %d wires%s", config->pins[0], is_usb0_device(config) ? " (dev)" : ""); if (config->pins[1]) printk(", usb1 %d wires", config->pins[1]); if (!alt_pingroup && config->pins[2]) printk(", usb2 %d wires", config->pins[2]); if (config->otg) printk(", Mini-AB on usb%d", config->otg - 1); printk("\n"); if (cpu_class_is_omap1()) { u16 w; /* leave USB clocks/controllers off until needed */ w = omap_readw(ULPD_SOFT_REQ); w &= ~SOFT_USB_CLK_REQ; omap_writew(w, ULPD_SOFT_REQ); w = omap_readw(ULPD_CLOCK_CTRL); w &= ~USB_MCLK_EN; w |= DIS_USB_PVCI_CLK; omap_writew(w, ULPD_CLOCK_CTRL); } syscon = omap_readl(OTG_SYSCON_1); syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN; #ifdef CONFIG_USB_GADGET_OMAP if (config->otg || config->register_dev) { syscon &= ~DEV_IDLE_EN; udc_device.dev.platform_data = config; /* FIXME patch IRQ numbers for omap730 */ status = platform_device_register(&udc_device); if (status) pr_debug("can't register UDC device, %d\n", status); } #endif #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) if (config->otg || config->register_host) { syscon &= ~HST_IDLE_EN; ohci_device.dev.platform_data = config; if (cpu_is_omap730()) ohci_resources[1].start = INT_730_USB_HHC_1; status = platform_device_register(&ohci_device); if (status) pr_debug("can't register OHCI device, %d\n", status); } #endif #ifdef CONFIG_USB_OTG if (config->otg) { syscon &= ~OTG_IDLE_EN; otg_device.dev.platform_data = config; if (cpu_is_omap730()) otg_resources[1].start = INT_730_USB_OTG; status = platform_device_register(&otg_device); if (status) pr_debug("can't register OTG device, %d\n", status); } #endif pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); omap_writel(syscon, OTG_SYSCON_1); status = 0; }
/* * Note that on Innovator-1510 UART2 pins conflict with USB2. * By default UART2 does not work on Innovator-1510 if you have * USB OHCI enabled. To use UART2, you must disable USB2 first. */ void __init omap_serial_init(void) { int i; const struct omap_uart_config *info; if (cpu_is_omap730()) { serial_platform_data[0].regshift = 0; serial_platform_data[1].regshift = 0; serial_platform_data[0].irq = INT_730_UART_MODEM_1; serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2; } if (cpu_is_omap1510()) { serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16; serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16; serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16; } info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config); if (info == NULL) return; for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { unsigned char reg; if (!((1 << i) & info->enabled_uarts)) { serial_platform_data[i].membase = NULL; serial_platform_data[i].mapbase = 0; continue; } switch (i) { case 0: uart1_ck = clk_get(NULL, "uart1_ck"); if (IS_ERR(uart1_ck)) printk("Could not get uart1_ck\n"); else { clk_use(uart1_ck); if (cpu_is_omap1510()) clk_set_rate(uart1_ck, 12000000); } if (cpu_is_omap1510()) { omap_cfg_reg(UART1_TX); omap_cfg_reg(UART1_RTS); if (machine_is_omap_innovator()) { reg = fpga_read(OMAP1510_FPGA_POWER); reg |= OMAP1510_FPGA_PCR_COM1_EN; fpga_write(reg, OMAP1510_FPGA_POWER); udelay(10); } } break; case 1: uart2_ck = clk_get(NULL, "uart2_ck"); if (IS_ERR(uart2_ck)) printk("Could not get uart2_ck\n"); else { clk_use(uart2_ck); if (cpu_is_omap1510()) clk_set_rate(uart2_ck, 12000000); else clk_set_rate(uart2_ck, 48000000); } if (cpu_is_omap1510()) { omap_cfg_reg(UART2_TX); omap_cfg_reg(UART2_RTS); if (machine_is_omap_innovator()) { reg = fpga_read(OMAP1510_FPGA_POWER); reg |= OMAP1510_FPGA_PCR_COM2_EN; fpga_write(reg, OMAP1510_FPGA_POWER); udelay(10); } } break; case 2: uart3_ck = clk_get(NULL, "uart3_ck"); if (IS_ERR(uart3_ck)) printk("Could not get uart3_ck\n"); else { clk_use(uart3_ck); if (cpu_is_omap1510()) clk_set_rate(uart3_ck, 12000000); } if (cpu_is_omap1510()) { omap_cfg_reg(UART3_TX); omap_cfg_reg(UART3_RX); } break; } omap_serial_reset(&serial_platform_data[i]); } }
void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type) { #ifdef CONFIG_ARCH_OMAP1 if (cpu_class_is_omap1()) { if (BETWEEN(p, OMAP1_IO_PHYS, OMAP1_IO_SIZE)) return XLATE(p, OMAP1_IO_PHYS, OMAP1_IO_VIRT); } if (cpu_is_omap730()) { if (BETWEEN(p, OMAP730_DSP_BASE, OMAP730_DSP_SIZE)) return XLATE(p, OMAP730_DSP_BASE, OMAP730_DSP_START); if (BETWEEN(p, OMAP730_DSPREG_BASE, OMAP730_DSPREG_SIZE)) return XLATE(p, OMAP730_DSPREG_BASE, OMAP730_DSPREG_START); } if (cpu_is_omap15xx()) { if (BETWEEN(p, OMAP1510_DSP_BASE, OMAP1510_DSP_SIZE)) return XLATE(p, OMAP1510_DSP_BASE, OMAP1510_DSP_START); if (BETWEEN(p, OMAP1510_DSPREG_BASE, OMAP1510_DSPREG_SIZE)) return XLATE(p, OMAP1510_DSPREG_BASE, OMAP1510_DSPREG_START); } if (cpu_is_omap16xx()) { if (BETWEEN(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_SIZE)) return XLATE(p, OMAP16XX_DSP_BASE, OMAP16XX_DSP_START); if (BETWEEN(p, OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_SIZE)) return XLATE(p, OMAP16XX_DSPREG_BASE, OMAP16XX_DSPREG_START); } #endif #ifdef CONFIG_ARCH_OMAP2 if (cpu_is_omap24xx()) { if (BETWEEN(p, L3_24XX_PHYS, L3_24XX_SIZE)) return XLATE(p, L3_24XX_PHYS, L3_24XX_VIRT); if (BETWEEN(p, L4_24XX_PHYS, L4_24XX_SIZE)) return XLATE(p, L4_24XX_PHYS, L4_24XX_VIRT); } if (cpu_is_omap2420()) { if (BETWEEN(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_SIZE)) return XLATE(p, DSP_MEM_24XX_PHYS, DSP_MEM_24XX_VIRT); if (BETWEEN(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE)) return XLATE(p, DSP_IPI_24XX_PHYS, DSP_IPI_24XX_SIZE); if (BETWEEN(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_SIZE)) return XLATE(p, DSP_MMU_24XX_PHYS, DSP_MMU_24XX_VIRT); } if (cpu_is_omap2430()) { if (BETWEEN(p, L4_WK_243X_PHYS, L4_WK_243X_SIZE)) return XLATE(p, L4_WK_243X_PHYS, L4_WK_243X_VIRT); if (BETWEEN(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_SIZE)) return XLATE(p, OMAP243X_GPMC_PHYS, OMAP243X_GPMC_VIRT); if (BETWEEN(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_SIZE)) return XLATE(p, OMAP243X_SDRC_PHYS, OMAP243X_SDRC_VIRT); if (BETWEEN(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_SIZE)) return XLATE(p, OMAP243X_SMS_PHYS, OMAP243X_SMS_VIRT); } #endif #ifdef CONFIG_ARCH_OMAP3 if (cpu_is_omap34xx()) { if (BETWEEN(p, L3_34XX_PHYS, L3_34XX_SIZE)) return XLATE(p, L3_34XX_PHYS, L3_34XX_VIRT); if (BETWEEN(p, L4_34XX_PHYS, L4_34XX_SIZE)) return XLATE(p, L4_34XX_PHYS, L4_34XX_VIRT); if (BETWEEN(p, L4_WK_34XX_PHYS, L4_WK_34XX_SIZE)) return XLATE(p, L4_WK_34XX_PHYS, L4_WK_34XX_VIRT); if (BETWEEN(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_SIZE)) return XLATE(p, OMAP34XX_GPMC_PHYS, OMAP34XX_GPMC_VIRT); if (BETWEEN(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_SIZE)) return XLATE(p, OMAP343X_SMS_PHYS, OMAP343X_SMS_VIRT); if (BETWEEN(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_SIZE)) return XLATE(p, OMAP343X_SDRC_PHYS, OMAP343X_SDRC_VIRT); if (BETWEEN(p, L4_PER_34XX_PHYS, L4_PER_34XX_SIZE)) return XLATE(p, L4_PER_34XX_PHYS, L4_PER_34XX_VIRT); if (BETWEEN(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_SIZE)) return XLATE(p, L4_EMU_34XX_PHYS, L4_EMU_34XX_VIRT); } #endif #ifdef CONFIG_ARCH_OMAP4 if (cpu_is_omap44xx()) { if (BETWEEN(p, L3_44XX_PHYS, L3_44XX_SIZE)) return XLATE(p, L3_44XX_PHYS, L3_44XX_VIRT); if (BETWEEN(p, L4_44XX_PHYS, L4_44XX_SIZE)) return XLATE(p, L4_44XX_PHYS, L4_44XX_VIRT); if (BETWEEN(p, L4_WK_44XX_PHYS, L4_WK_44XX_SIZE)) return XLATE(p, L4_WK_44XX_PHYS, L4_WK_44XX_VIRT); if (BETWEEN(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_SIZE)) return XLATE(p, OMAP44XX_GPMC_PHYS, OMAP44XX_GPMC_VIRT); if (BETWEEN(p, L4_PER_44XX_PHYS, L4_PER_44XX_SIZE)) return XLATE(p, L4_PER_44XX_PHYS, L4_PER_44XX_VIRT); if (BETWEEN(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_SIZE)) return XLATE(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_VIRT); } #endif return __arm_ioremap(p, size, type); }
/* * Note that on Innovator-1510 UART2 pins conflict with USB2. * By default UART2 does not work on Innovator-1510 if you have * USB OHCI enabled. To use UART2, you must disable USB2 first. */ void __init omap_serial_init(void) { int i; if (cpu_is_omap730()) { serial_platform_data[0].regshift = 0; serial_platform_data[1].regshift = 0; serial_platform_data[0].irq = INT_730_UART_MODEM_1; serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2; } if (cpu_is_omap850()) { serial_platform_data[0].regshift = 0; serial_platform_data[1].regshift = 0; serial_platform_data[0].irq = INT_850_UART_MODEM_1; serial_platform_data[1].irq = INT_850_UART_MODEM_IRDA_2; } if (cpu_is_omap15xx()) { serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16; serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16; serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16; } for (i = 0; i < OMAP_MAX_NR_PORTS; i++) { switch (i) { case 0: uart1_ck = clk_get(NULL, "uart1_ck"); if (IS_ERR(uart1_ck)) printk("Could not get uart1_ck\n"); else { clk_enable(uart1_ck); if (cpu_is_omap15xx()) clk_set_rate(uart1_ck, 12000000); } break; case 1: uart2_ck = clk_get(NULL, "uart2_ck"); if (IS_ERR(uart2_ck)) printk("Could not get uart2_ck\n"); else { clk_enable(uart2_ck); if (cpu_is_omap15xx()) clk_set_rate(uart2_ck, 12000000); else clk_set_rate(uart2_ck, 48000000); } break; case 2: uart3_ck = clk_get(NULL, "uart3_ck"); if (IS_ERR(uart3_ck)) printk("Could not get uart3_ck\n"); else { clk_enable(uart3_ck); if (cpu_is_omap15xx()) clk_set_rate(uart3_ck, 12000000); } break; } omap_serial_reset(&serial_platform_data[i]); } }
void __init omap_init_irq(void) { int i, j; #ifdef CONFIG_ARCH_OMAP730 if (cpu_is_omap730()) { irq_banks = omap730_irq_banks; irq_bank_count = ARRAY_SIZE(omap730_irq_banks); } #endif #ifdef CONFIG_ARCH_OMAP15XX if (cpu_is_omap1510()) { irq_banks = omap1510_irq_banks; irq_bank_count = ARRAY_SIZE(omap1510_irq_banks); } if (cpu_is_omap310()) { irq_banks = omap310_irq_banks; irq_bank_count = ARRAY_SIZE(omap310_irq_banks); } #endif #if defined(CONFIG_ARCH_OMAP16XX) if (cpu_is_omap16xx()) { irq_banks = omap1610_irq_banks; irq_bank_count = ARRAY_SIZE(omap1610_irq_banks); } #endif printk("Total of %i interrupts in %i interrupt banks\n", irq_bank_count * 32, irq_bank_count); /* Mask and clear all interrupts */ for (i = 0; i < irq_bank_count; i++) { irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET); irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET); } /* Clear any pending interrupts */ irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET); irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET); /* Enable interrupts in global mask */ if (cpu_is_omap730()) { irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET); } /* Install the interrupt handlers for each bank */ for (i = 0; i < irq_bank_count; i++) { for (j = i * 32; j < (i + 1) * 32; j++) { int irq_trigger; irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); omap_irq_set_cfg(j, 0, 0, irq_trigger); set_irq_chip(j, &omap_irq_chip); set_irq_handler(j, handle_level_irq); set_irq_flags(j, IRQF_VALID); } } /* Unmask level 2 handler */ if (cpu_is_omap730()) omap_unmask_irq(INT_730_IH2_IRQ); else if (cpu_is_omap15xx()) omap_unmask_irq(INT_1510_IH2_IRQ); else if (cpu_is_omap16xx()) omap_unmask_irq(INT_1610_IH2_IRQ); }