/*
* Called from the suspend/resume path to only keep the real wakeup interrupts
* (those that have had set_irq_wake() called on them) as wakeup interrupts,
* and not the rest of the interrupts which we needed to have as wakeups for
* cpuidle.
*
* PM ops are not used since this needs to be done at the end, after all the
* other drivers are done with their suspend callbacks.
*/
void nmk_gpio_wakeups_suspend(void)
{
int i;
for (i = 0; i < NUM_BANKS; i++) {
struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
if (!chip)
break;
chip->rwimsc = readl(chip->addr + NMK_GPIO_RWIMSC);
chip->fwimsc = readl(chip->addr + NMK_GPIO_FWIMSC);
writel(chip->rwimsc & chip->real_wake,
chip->addr + NMK_GPIO_RWIMSC);
writel(chip->fwimsc & chip->real_wake,
chip->addr + NMK_GPIO_FWIMSC);
if (cpu_is_u8500v2()) {
chip->slpm = readl(chip->addr + NMK_GPIO_SLPC);
/* 0 -> wakeup enable */
writel(~chip->real_wake, chip->addr + NMK_GPIO_SLPC);
}
}
}
static void __init db8500_add_gpios(void)
{
struct nmk_gpio_platform_data pdata = {
/* No custom data yet */
};
if (cpu_is_u8500v2())
pdata.supports_sleepmode = true;
dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base),
IRQ_DB8500_GPIO0, &pdata);
}
/* Main clock init function. Called from arch_cpu_init() */
void db8500_clocks_init(void)
{
/*
* Enable all clocks. This is u-boot, we can enable it all. There is no
* powersave in u-boot.
*/
clock_enable(1, 9, -1); /* GPIO0 */
if (u8500_is_earlydrop())
clock_enable(2, 12, -1); /* GPIO1 */
else
clock_enable(2, 11, -1); /* GPIO1 */
clock_enable(3, 8, -1); /* GPIO2 */
clock_enable(5, 1, -1); /* GPIO3 */
clock_enable(3, 6, 6); /* UART2 */
clock_enable(3, 3, 3); /* I2C0 */
clock_enable(1, 5, 5); /* SDI0 */
clock_enable(2, 4, 2); /* SDI4 */
if (u8500_is_earlydrop())
clock_enable(7, 2, -1); /* MTU0 */
else if (cpu_is_u8500v1())
clock_enable(6, 7, -1); /* MTU0 */
else if (cpu_is_u8500v2() || cpu_is_u9540v10())
clock_enable(6, 6, -1); /* MTU0 */
if (!u8500_is_earlydrop())
clock_enable(3, 4, 4); /* SDI2 */
/*
* Enabling clocks for all devices which are AMBA devices in the
* kernel. Otherwise they will not get probe()'d because the
* peripheral ID register will not be powered.
*/
/* XXX: some of these differ between ED/V1 */
clock_enable(1, 1, 1); /* UART1 */
clock_enable(1, 0, 0); /* UART0 */
clock_enable(3, 2, 2); /* SSP1 */
clock_enable(3, 1, 1); /* SSP0 */
clock_enable(2, 8, -1); /* SPI0 */
clock_enable(2, 5, 3); /* MSP2 */
}
void nmk_gpio_wakeups_resume(void)
{
int i;
for (i = 0; i < NUM_BANKS; i++) {
struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
if (!chip)
break;
writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
if (cpu_is_u8500v2())
writel(chip->slpm, chip->addr + NMK_GPIO_SLPC);
}
}
void __init u8500_map_io(void)
{
/*
* Map the UARTs early so that the DEBUG_LL stuff continues to work.
*/
iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc));
ux500_map_io();
iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
if (cpu_is_u8500ed())
iotable_init(u8500_ed_io_desc, ARRAY_SIZE(u8500_ed_io_desc));
else if (cpu_is_u8500v1())
iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc));
else if (cpu_is_u8500v2())
iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc));
_PRCMU_BASE = __io_address(U8500_PRCMU_BASE);
}