/*
dpy iot callback
Light on one pixel on CRT
*/
static void iot_dpy(device_t *device, int op2, int nac, int mb, int *io, int ac)
{
pdp1_state *state = device->machine().driver_data<pdp1_state>();
int x;
int y;
x = ((ac+0400000) & 0777777) >> 8;
y = (((*io)+0400000) & 0777777) >> 8;
pdp1_plot(device->machine(), x, y);
/* light pen 32 support */
state->m_io_status &= ~io_st_pen;
if (state->m_lightpen.down && ((x-state->m_lightpen.x)*(x-state->m_lightpen.x)+(y-state->m_lightpen.y)*(y-state->m_lightpen.y) < state->m_lightpen.radius*state->m_lightpen.radius))
{
state->m_io_status |= io_st_pen;
cpu_set_reg(device->machine().device("maincpu"), PDP1_PF3, 1);
}
if (nac)
{
/* 50us delay */
if (LOG_IOT_OVERLAP)
{
/* note that overlap detection is incomplete: it will only work if both DPY
instructions require a completion pulse */
if (state->m_dpy_timer->enable(0))
logerror("Error: overlapped DPY instruction: mb=0%06o, (%s)\n", (unsigned) mb, device->machine().describe_context());
}
state->m_dpy_timer->adjust(attotime::from_usec(50));
}
}
static void mxtc_config_w(device_t *busdevice, device_t *device, int function, int reg, UINT8 data)
{
calchase_state *state = busdevice->machine().driver_data<calchase_state>();
// mame_printf_debug("%s:MXTC: write %d, %02X, %02X\n", machine.describe_context(), function, reg, data);
switch(reg)
{
//case 0x59:
case 0x63: // PAM0
{
//if (data & 0x10) // enable RAM access to region 0xf0000 - 0xfffff
if ((data & 0x50) | (data & 0xA0))
{
state->membank("bank1")->set_base(state->m_bios_ram);
}
else // disable RAM access (reads go to BIOS ROM)
{
//Execution Hack to avoid crash when switch back from Shadow RAM to Bios ROM, since i386 emu haven't yet pipelined execution structure.
//It happens when exit from BIOS SETUP.
#if 0
if ((state->m_mxtc_config_reg[0x63] & 0x50) | ( state->m_mxtc_config_reg[0x63] & 0xA0)) // Only DO if comes a change to disable ROM.
{
if ( cpu_get_pc(busdevice->machine().device("maincpu"))==0xff74e) cpu_set_reg(busdevice->machine().device("maincpu"), STATE_GENPC, 0xff74d);
}
#endif
state->membank("bank1")->set_base(busdevice->machine().root_device().memregion("bios")->base() + 0x10000);
state->membank("bank1")->set_base(busdevice->machine().root_device().memregion("bios")->base());
}
break;
}
}
state->m_mxtc_config_reg[reg] = data;
}
INPUT_PORTS_END
static MACHINE_RESET(horizon)
{
cpu_set_reg(machine.device("maincpu"), Z80_PC, 0xe800);
}
INPUT_PORTS_END
static MACHINE_RESET(ipc)
{
cpu_set_reg(machine.device("maincpu"), I8085_PC, 0xE800);
}
/* this function checks the cache to see if the current state is cached,
if it is then it copies the cached data to the user region where code is
executed from, if its not cached then it gets decrypted to the current
cache position using the functions in s24_fd1094.c */
static void s24_fd1094_setstate_and_decrypt(running_machine *machine, int state)
{
int i;
UINT32 addr;
switch (state & 0x300)
{
case 0x000:
case FD1094_STATE_RESET:
fd1094_selected_state = state & 0xff;
break;
}
fd1094_state = state;
cpu_set_reg(machine->device("sub"), M68K_PREF_ADDR, 0x0010); // force a flush of the prefetch cache
/* set the s24_fd1094 state ready to decrypt.. */
state = fd1094_set_state(s24_fd1094_key,state) & 0xff;
/* first check the cache, if its cached we don't need to decrypt it, just copy */
for (i = 0; i < S16_NUMCACHE; i++)
{
if (fd1094_cached_states[i] == state)
{
/* copy cached state */
s24_fd1094_userregion = s24_fd1094_cacheregion[i];
machine->device<cpu_device>("sub")->space(AS_PROGRAM)->set_decrypted_region(0, s24_fd1094_cpuregionsize - 1, s24_fd1094_userregion);
m68k_set_encrypted_opcode_range(machine->device("sub"), 0, s24_fd1094_cpuregionsize);
return;
}
}
// mame_printf_debug("new state %04x\n",state);
/* mark it as cached (because it will be once we decrypt it) */
fd1094_cached_states[fd1094_current_cacheposition] = state;
for (addr = 0; addr < s24_fd1094_cpuregionsize / 2; addr++)
{
UINT16 dat;
dat = fd1094_decode(addr, s24_fd1094_cpuregion[addr], s24_fd1094_key, 0);
s24_fd1094_cacheregion[fd1094_current_cacheposition][addr] = dat;
}
/* copy newly decrypted data to user region */
s24_fd1094_userregion = s24_fd1094_cacheregion[fd1094_current_cacheposition];
machine->device<cpu_device>("sub")->space(AS_PROGRAM)->set_decrypted_region(0, s24_fd1094_cpuregionsize - 1, s24_fd1094_userregion);
m68k_set_encrypted_opcode_range(machine->device("sub"), 0, s24_fd1094_cpuregionsize);
fd1094_current_cacheposition++;
if (fd1094_current_cacheposition >= S16_NUMCACHE)
{
mame_printf_debug("out of cache, performance may suffer, incrase S16_NUMCACHE!\n");
fd1094_current_cacheposition = 0;
}
}
static MACHINE_RESET(altair)
{
altair_state *state = machine.driver_data<altair_state>();
// Set startup addess done by turn-key
cpu_set_reg(machine.device("maincpu"), I8085_PC, 0xFD00);
state->m_term_data = 0;
}
/* this function checks the cache to see if the current state is cached,
if it is then it copies the cached data to the user region where code is
executed from, if its not cached then it gets decrypted to the current
cache position using the functions in fd1094.c */
static void fd1094_setstate_and_decrypt(running_machine &machine, int state)
{
int i;
UINT32 addr;
switch (state & 0x300)
{
case 0x000:
case FD1094_STATE_RESET:
fd1094_selected_state = state & 0xff;
break;
}
fd1094_state = state;
cpu_set_reg(machine.device(fd1094_cputag), M68K_PREF_ADDR, 0x0010); // force a flush of the prefetch cache
/* set the FD1094 state ready to decrypt.. */
state = fd1094_set_state(fd1094_key, state) & 0xff;
/* first check the cache, if its cached we don't need to decrypt it, just copy */
for (i = 0; i < CACHE_ENTRIES; i++)
{
if (fd1094_cached_states[i] == state)
{
/* copy cached state */
fd1094_userregion = fd1094_cacheregion[i];
set_decrypted_region(machine);
m68k_set_encrypted_opcode_range(machine.device(fd1094_cputag), 0, fd1094_cpuregionsize);
return;
}
}
/* mark it as cached (because it will be once we decrypt it) */
fd1094_cached_states[fd1094_current_cacheposition] = state;
for (addr = 0; addr < fd1094_cpuregionsize / 2; addr++)
{
UINT16 dat;
dat = fd1094_decode(addr,fd1094_cpuregion[addr],fd1094_key,0);
fd1094_cacheregion[fd1094_current_cacheposition][addr]=dat;
}
/* copy newly decrypted data to user region */
fd1094_userregion = fd1094_cacheregion[fd1094_current_cacheposition];
set_decrypted_region(machine);
m68k_set_encrypted_opcode_range(machine.device(fd1094_cputag), 0, fd1094_cpuregionsize);
fd1094_current_cacheposition++;
if (fd1094_current_cacheposition >= CACHE_ENTRIES)
{
mame_printf_debug("out of cache, performance may suffer, incrase CACHE_ENTRIES!\n");
fd1094_current_cacheposition = 0;
}
}
INPUT_PORTS_END
static MACHINE_RESET(vector4)
{
vector4_state *state = machine.driver_data<vector4_state>();
state->m_term_data = 0;
cpu_set_reg(machine.device("maincpu"), Z80_PC, 0xe000);
}
/*
timer callback to simulate reader IO
*/
static TIMER_CALLBACK(reader_callback)
{
pdp1_state *state = machine.driver_data<pdp1_state>();
int not_ready;
UINT8 data;
if (state->m_tape_reader.rc)
{
not_ready = tape_read(state, & data);
if (not_ready)
{
state->m_tape_reader.motor_on = 0; /* let us stop the motor */
}
else
{
if ((! state->m_tape_reader.rby) || (data & 0200))
{
state->m_tape_reader.rb |= (state->m_tape_reader.rby) ? (data & 077) : data;
if (state->m_tape_reader.rc != 3)
{
state->m_tape_reader.rb <<= 6;
}
state->m_tape_reader.rc = (state->m_tape_reader.rc+1) & 3;
if (state->m_tape_reader.rc == 0)
{ /* IO complete */
state->m_tape_reader.rcl = 0;
if (state->m_tape_reader.rcp)
{
cpu_set_reg(machine.device("maincpu"), PDP1_IO, state->m_tape_reader.rb); /* transfer reader buffer to IO */
pdp1_pulse_iot_done(machine.device("maincpu"));
}
else
state->m_io_status |= io_st_ptr;
}
}
}
}
if (state->m_tape_reader.motor_on && state->m_tape_reader.rcl)
/* delay is approximately 1/400s */
state->m_tape_reader.timer->adjust(attotime::from_usec(2500));
else
state->m_tape_reader.timer->enable(0);
}
void alphatro_state::machine_reset()
{
// do what the IPL does
// UINT8* RAM = machine().device<ram_device>("ram")->pointer();
UINT8* ROM = memregion("maincpu")->base();
cpu_set_reg(m_maincpu, STATE_GENPC, 0xe000);
memcpy(m_p_ram, ROM, 0xf000); // copy BASIC to RAM, which the undumped IPL is supposed to do.
memcpy(m_p_videoram, ROM+0x1000, 0x1000);
// membank("bank1")->set_base(RAM);
// probably not correct, exact meaning of port is unknown, vblank/vsync is too slow.
m_sys_timer->adjust(attotime::from_usec(10),0,attotime::from_usec(10));
m_serial_timer->adjust(attotime::from_hz(500),0,attotime::from_hz(500)); // USART clock - this is a guesstimate
m_timer_bit = 0;
beep_set_state(m_beep, 0);
beep_set_frequency(m_beep, 950); /* piezo-device needs to be measured */
}
static MACHINE_RESET( jaguar )
{
device_set_irq_callback(machine.device("maincpu"), jaguar_irq_callback);
protection_check = 0;
/* Set up pointers for Jaguar logo */
memcpy(jaguar_shared_ram, rom_base, 0x400); // do not increase, or Doom breaks
cpu_set_reg(machine.device("maincpu"), STATE_GENPC, rom_base[1]);
#if 0
/* set up main CPU RAM/ROM banks */
memory_set_bankptr(machine, 3, jaguar_gpu_ram);
/* set up DSP RAM/ROM banks */
memory_set_bankptr(machine, 10, jaguar_shared_ram);
memory_set_bankptr(machine, 11, jaguar_gpu_clut);
memory_set_bankptr(machine, 12, jaguar_gpu_ram);
memory_set_bankptr(machine, 13, jaguar_dsp_ram);
memory_set_bankptr(machine, 14, jaguar_shared_ram);
memory_set_bankptr(machine, 15, cart_base);
memory_set_bankptr(machine, 16, rom_base);
memory_set_bankptr(machine, 17, jaguar_gpu_ram);
#endif
/* clear any spinuntil stuff */
jaguar_gpu_resume(machine);
jaguar_dsp_resume(machine);
/* halt the CPUs */
jaguargpu_ctrl_w(machine.device("gpu"), G_CTRL, 0, 0xffffffff);
jaguardsp_ctrl_w(machine.device("audiocpu"), D_CTRL, 0, 0xffffffff);
joystick_data = 0xffffffff;
eeprom_bit_count = 0;
blitter_status = 1;
if ((using_cart) && (input_port_read(machine, "CONFIG") & 2))
{
cart_base[0x102] = 1;
using_cart = 0;
}
}
static void cpe_set_register( device_t *cpu, int n_reg, int n_value )
{
if( n_reg < 0x80 && ( n_reg % 4 ) == 0 )
{
logerror( "psx_exe_load: r%-2d %08x\n", n_reg / 4, n_value );
cpu_set_reg( cpu, PSXCPU_R0 + ( n_reg / 4 ), n_value );
}
else if( n_reg == 0x80 )
{
logerror( "psx_exe_load: lo %08x\n", n_value );
cpu_set_reg( cpu, PSXCPU_LO, n_value );
}
else if( n_reg == 0x84 )
{
logerror( "psx_exe_load: hi %08x\n", n_value );
cpu_set_reg( cpu, PSXCPU_HI, n_value );
}
else if( n_reg == 0x88 )
{
logerror( "psx_exe_load: sr %08x\n", n_value );
cpu_set_reg( cpu, PSXCPU_CP0R12, n_value );
}
else if( n_reg == 0x8c )
{
logerror( "psx_exe_load: cause %08x\n", n_value );
cpu_set_reg( cpu, PSXCPU_CP0R13, n_value );
}
else if( n_reg == 0x90 )
{
logerror( "psx_exe_load: pc %08x\n", n_value );
cpu_set_reg( cpu, PSXCPU_PC, n_value );
}
else if( n_reg == 0x94 )
{
logerror( "psx_exe_load: prid %08x\n", n_value );
cpu_set_reg( cpu, PSXCPU_CP0R15, n_value );
}
else
{
logerror( "psx_exe_load: invalid register %04x/%08x\n", n_reg, n_value );
}
}
static MACHINE_RESET(pdp11ub2)
{
// Load M9312
UINT8* user1 = machine.region("user1")->base();
UINT8* maincpu = machine.region("maincpu")->base();
int i;
// 3 2 1 8
// 7 6 5 4
// ~11 ~10 9 0
// 15 14 13 ~12
for(i=0;i<0x100;i++) {
UINT8 nib1 = user1[i*4+0];
UINT8 nib2 = user1[i*4+1];
UINT8 nib3 = user1[i*4+2];
UINT8 nib4 = user1[i*4+3];
maincpu[0xea00 + i*2 + 0] = (nib2 << 4) + ((nib1 & 0x0e) | (nib3 & 1));
maincpu[0xea00 + i*2 + 1] = ((nib4 ^ 0x01)<<4) + ((nib1 & 0x01) | ((nib3 ^ 0x0c) & 0x0e));
}
cpu_set_reg(machine.device("maincpu"), T11_PC, 0xea10); // diag*/
//cpu_set_reg(machine.device("maincpu"), T11_PC, 0xea64); // no-diag
}
static int load_psxexe( device_t *cpu, unsigned char *p_n_file, int n_len )
{
psx_state *state = cpu->machine().driver_data<psx_state>();
struct PSXEXE_HEADER
{
UINT8 id[ 8 ];
UINT32 text; /* SCE only */
UINT32 data; /* SCE only */
UINT32 pc0;
UINT32 gp0; /* SCE only */
UINT32 t_addr;
UINT32 t_size;
UINT32 d_addr; /* SCE only */
UINT32 d_size; /* SCE only */
UINT32 b_addr; /* SCE only */
UINT32 b_size; /* SCE only */
UINT32 s_addr;
UINT32 s_size;
UINT32 SavedSP;
UINT32 SavedFP;
UINT32 SavedGP;
UINT32 SavedRA;
UINT32 SavedS0;
UINT8 dummy[ 0x800 - 76 ];
};
struct PSXEXE_HEADER *psxexe_header = (struct PSXEXE_HEADER *)p_n_file;
if( n_len >= sizeof( struct PSXEXE_HEADER ) &&
memcmp( psxexe_header->id, "PS-X EXE", 8 ) == 0 )
{
UINT8 *p_ram;
UINT8 *p_psxexe;
UINT32 n_stack;
UINT32 n_ram;
UINT32 n_address;
UINT32 n_size;
psxexe_conv32( &psxexe_header->text );
psxexe_conv32( &psxexe_header->data );
psxexe_conv32( &psxexe_header->pc0 );
psxexe_conv32( &psxexe_header->gp0 );
psxexe_conv32( &psxexe_header->t_addr );
psxexe_conv32( &psxexe_header->t_size );
psxexe_conv32( &psxexe_header->d_addr );
psxexe_conv32( &psxexe_header->d_size );
psxexe_conv32( &psxexe_header->b_addr );
psxexe_conv32( &psxexe_header->b_size );
psxexe_conv32( &psxexe_header->s_addr );
psxexe_conv32( &psxexe_header->s_size );
psxexe_conv32( &psxexe_header->SavedSP );
psxexe_conv32( &psxexe_header->SavedFP );
psxexe_conv32( &psxexe_header->SavedGP );
psxexe_conv32( &psxexe_header->SavedRA );
psxexe_conv32( &psxexe_header->SavedS0 );
/* todo: check size.. */
logerror( "psx_exe_load: pc %08x\n", psxexe_header->pc0 );
logerror( "psx_exe_load: org %08x\n", psxexe_header->t_addr );
logerror( "psx_exe_load: len %08x\n", psxexe_header->t_size );
logerror( "psx_exe_load: sp %08x\n", psxexe_header->s_addr );
logerror( "psx_exe_load: len %08x\n", psxexe_header->s_size );
p_ram = (UINT8 *)state->m_p_n_psxram;
n_ram = state->m_n_psxramsize;
p_psxexe = p_n_file + sizeof( struct PSXEXE_HEADER );
n_address = psxexe_header->t_addr;
n_size = psxexe_header->t_size;
while( n_size != 0 )
{
p_ram[ BYTE4_XOR_LE( n_address ) % n_ram ] = *( p_psxexe );
n_address++;
p_psxexe++;
n_size--;
}
cpu_set_reg( cpu, PSXCPU_PC, psxexe_header->pc0 );
cpu_set_reg( cpu, PSXCPU_R28, psxexe_header->gp0 );
n_stack = psxexe_header->s_addr + psxexe_header->s_size;
if( n_stack != 0 )
{
cpu_set_reg( cpu, PSXCPU_R29, n_stack );
cpu_set_reg( cpu, PSXCPU_R30, n_stack );
}
return 1;
}
return 0;
}
static void galaxy_setup_snapshot (running_machine &machine, const UINT8 * data, UINT32 size)
{
device_t *cpu = machine.device("maincpu");
switch (size)
{
case GALAXY_SNAPSHOT_V1_SIZE:
cpu_set_reg(cpu, Z80_AF, data[0x00] | data[0x01] << 8);
cpu_set_reg(cpu, Z80_BC, data[0x04] | data[0x05] << 8);
cpu_set_reg(cpu, Z80_DE, data[0x08] | data[0x09] << 8);
cpu_set_reg(cpu, Z80_HL, data[0x0c] | data[0x0d] << 8);
cpu_set_reg(cpu, Z80_IX, data[0x10] | data[0x11] << 8);
cpu_set_reg(cpu, Z80_IY, data[0x14] | data[0x15] << 8);
cpu_set_reg(cpu, Z80_PC, data[0x18] | data[0x19] << 8);
cpu_set_reg(cpu, Z80_SP, data[0x1c] | data[0x1d] << 8);
cpu_set_reg(cpu, Z80_AF2, data[0x20] | data[0x21] << 8);
cpu_set_reg(cpu, Z80_BC2, data[0x24] | data[0x25] << 8);
cpu_set_reg(cpu, Z80_DE2, data[0x28] | data[0x29] << 8);
cpu_set_reg(cpu, Z80_HL2, data[0x2c] | data[0x2d] << 8);
cpu_set_reg(cpu, Z80_IFF1, data[0x30]);
cpu_set_reg(cpu, Z80_IFF2, data[0x34]);
cpu_set_reg(cpu, Z80_HALT, data[0x38]);
cpu_set_reg(cpu, Z80_IM, data[0x3c]);
cpu_set_reg(cpu, Z80_I, data[0x40]);
cpu_set_reg(cpu, Z80_R, (data[0x44] & 0x7f) | (data[0x48] & 0x80));
memcpy (ram_get_ptr(machine.device(RAM_TAG)), data + 0x084c, (ram_get_size(machine.device(RAM_TAG)) < 0x1800) ? ram_get_size(machine.device(RAM_TAG)) : 0x1800);
break;
case GALAXY_SNAPSHOT_V2_SIZE:
cpu_set_reg(cpu, Z80_AF, data[0x00] | data[0x01] << 8);
cpu_set_reg(cpu, Z80_BC, data[0x02] | data[0x03] << 8);
cpu_set_reg(cpu, Z80_DE, data[0x04] | data[0x05] << 8);
cpu_set_reg(cpu, Z80_HL, data[0x06] | data[0x07] << 8);
cpu_set_reg(cpu, Z80_IX, data[0x08] | data[0x09] << 8);
cpu_set_reg(cpu, Z80_IY, data[0x0a] | data[0x0b] << 8);
cpu_set_reg(cpu, Z80_PC, data[0x0c] | data[0x0d] << 8);
cpu_set_reg(cpu, Z80_SP, data[0x0e] | data[0x0f] << 8);
cpu_set_reg(cpu, Z80_AF2, data[0x10] | data[0x11] << 8);
cpu_set_reg(cpu, Z80_BC2, data[0x12] | data[0x13] << 8);
cpu_set_reg(cpu, Z80_DE2, data[0x14] | data[0x15] << 8);
cpu_set_reg(cpu, Z80_HL2, data[0x16] | data[0x17] << 8);
cpu_set_reg(cpu, Z80_IFF1, data[0x18] & 0x01);
cpu_set_reg(cpu, Z80_IFF2, (UINT64)0);
cpu_set_reg(cpu, Z80_HALT, (UINT64)0);
cpu_set_reg(cpu, Z80_IM, (data[0x18] >> 1) & 0x03);
cpu_set_reg(cpu, Z80_I, data[0x19]);
cpu_set_reg(cpu, Z80_R, data[0x1a]);
memcpy (ram_get_ptr(machine.device(RAM_TAG)), data + 0x0834, (ram_get_size(machine.device(RAM_TAG)) < 0x1800) ? ram_get_size(machine.device(RAM_TAG)) : 0x1800);
break;
}
device_set_input_line(cpu, INPUT_LINE_NMI, CLEAR_LINE);
device_set_input_line(cpu, INPUT_LINE_IRQ0, CLEAR_LINE);
}
static MACHINE_RESET(pdp11qb)
{
cpu_set_reg(machine.device("maincpu"), T11_PC, 0xea00);
}
static MACHINE_RESET(mmd2)
{
cpu_set_reg(machine.device("maincpu"), I8085_PC, 0xd840); // fixme
}
static void ti8x_snapshot_setup_registers (running_machine &machine, UINT8 * data)
{
unsigned char lo,hi;
unsigned char * reg = data + 0x40;
/* Set registers */
lo = reg[0x00] & 0x0ff;
hi = reg[0x01] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_AF, (hi << 8) | lo);
lo = reg[0x04] & 0x0ff;
hi = reg[0x05] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_BC, (hi << 8) | lo);
lo = reg[0x08] & 0x0ff;
hi = reg[0x09] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_DE, (hi << 8) | lo);
lo = reg[0x0c] & 0x0ff;
hi = reg[0x0d] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_HL, (hi << 8) | lo);
lo = reg[0x10] & 0x0ff;
hi = reg[0x11] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_IX, (hi << 8) | lo);
lo = reg[0x14] & 0x0ff;
hi = reg[0x15] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_IY, (hi << 8) | lo);
lo = reg[0x18] & 0x0ff;
hi = reg[0x19] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_PC, (hi << 8) | lo);
lo = reg[0x1c] & 0x0ff;
hi = reg[0x1d] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_SP, (hi << 8) | lo);
lo = reg[0x20] & 0x0ff;
hi = reg[0x21] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_AF2, (hi << 8) | lo);
lo = reg[0x24] & 0x0ff;
hi = reg[0x25] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_BC2, (hi << 8) | lo);
lo = reg[0x28] & 0x0ff;
hi = reg[0x29] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_DE2, (hi << 8) | lo);
lo = reg[0x2c] & 0x0ff;
hi = reg[0x2d] & 0x0ff;
cpu_set_reg(machine.device("maincpu"), Z80_HL2, (hi << 8) | lo);
cpu_set_reg(machine.device("maincpu"), Z80_IFF1, reg[0x30]&0x0ff);
cpu_set_reg(machine.device("maincpu"), Z80_IFF2, reg[0x34]&0x0ff);
cpu_set_reg(machine.device("maincpu"), Z80_HALT, reg[0x38]&0x0ff);
cpu_set_reg(machine.device("maincpu"), Z80_IM, reg[0x3c]&0x0ff);
cpu_set_reg(machine.device("maincpu"), Z80_I, reg[0x40]&0x0ff);
cpu_set_reg(machine.device("maincpu"), Z80_R, (reg[0x44]&0x7f) | (reg[0x48]&0x80));
cputag_set_input_line(machine, "maincpu", 0, 0);
cputag_set_input_line(machine, "maincpu", INPUT_LINE_NMI, 0);
cputag_set_input_line(machine, "maincpu", INPUT_LINE_HALT, 0);
}
static MACHINE_RESET(horizon_sd)
{
cpu_set_reg(machine.device("maincpu"), Z80_PC, 0xe900);
}
