static void main_cpu_reset(void *opaque) { CPUCRISState *env = opaque; struct cris_load_info *li; li = env->load_info; cpu_state_reset(env); if (!li) { /* nothing more to do. */ return; } env->pc = li->entry; if (li->image_filename) { env->regs[8] = 0x56902387; /* RAM boot magic. */ env->regs[9] = 0x40004000 + li->image_size; } if (li->cmdline) { /* Let the kernel know we are modifying the cmdline. */ env->regs[10] = 0x87109563; env->regs[11] = 0x40000000; } }
static void riscv_cpu_reset(CPUState *s) { RISCVCPU *cpu = RISCV_CPU(s); RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); CPURISCVState *env = &cpu->env; mcc->parent_reset(s); tlb_flush(s, 1); cpu_state_reset(env); }
static void tricore_cpu_reset(CPUState *s) { TriCoreCPU *cpu = TRICORE_CPU(s); TriCoreCPUClass *tcc = TRICORE_CPU_GET_CLASS(cpu); CPUTriCoreState *env = &cpu->env; tcc->parent_reset(s); cpu_state_reset(env); }
static void main_cpu_reset(void *opaque) { ResetData *s = (ResetData *)opaque; CPUSPARCState *env = s->env; cpu_state_reset(env); env->halted = 0; env->pc = s->entry; env->npc = s->entry + 4; }
static void mpc8544ds_cpu_reset_sec(void *opaque) { CPUPPCState *env = opaque; cpu_state_reset(env); /* Secondary CPU starts in halted state for now. Needs to change when implementing non-kernel boot. */ env->halted = 1; env->exception_index = EXCP_HLT; }
/* CPUClass::reset() */ static void mips_cpu_reset(CPUState *s) { MIPSCPU *cpu = MIPS_CPU(s); MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); CPUMIPSState *env = &cpu->env; mcc->parent_reset(s); memset(env, 0, offsetof(CPUMIPSState, mvp)); tlb_flush(s, 1); cpu_state_reset(env); }
static void mpc8544ds_cpu_reset(void *opaque) { CPUPPCState *env = opaque; struct boot_info *bi = env->load_info; cpu_state_reset(env); /* Set initial guest state. */ env->halted = 0; env->gpr[1] = (16<<20) - 8; env->gpr[3] = bi->dt_base; env->nip = bi->entry; mmubooke_create_initial_mapping(env, 0, 0); }
static void main_cpu_reset(void *opaque) { ResetInfo *reset_info = opaque; CPULM32State *env = reset_info->env; cpu_state_reset(env); /* init defaults */ env->pc = reset_info->bootstrap_pc; env->regs[R_R1] = reset_info->cmdline_base; env->regs[R_R2] = reset_info->initrd_base; env->regs[R_R3] = reset_info->initrd_base + reset_info->initrd_size; env->eba = reset_info->flash_base; env->deba = reset_info->flash_base; }
/* CPUClass::reset() */ static void mips_cpu_reset(CPUState *s) { MIPSCPU *cpu = MIPS_CPU(s); MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); CPUMIPSState *env = &cpu->env; mcc->parent_reset(s); memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); cpu_state_reset(env); #ifndef CONFIG_USER_ONLY if (kvm_enabled()) { kvm_mips_reset_vcpu(cpu); } #endif }
/* CPUClass::reset() */ static void mips_cpu_reset(CPUState *s) { MIPSCPU *cpu = MIPS_CPU(s); MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); CPUMIPSState *env = &cpu->env; if (qemu_loglevel_mask(CPU_LOG_RESET)) { qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); log_cpu_state(env, 0); } mcc->parent_reset(s); memset(env, 0, offsetof(CPUMIPSState, breakpoints)); tlb_flush(env, 1); cpu_state_reset(env); }
static void main_cpu_reset(void *opaque) { ResetData *s = (ResetData *)opaque; CPUSPARCState *env = s->env; static unsigned int nr_resets; cpu_state_reset(env); cpu_timer_reset(env->tick); cpu_timer_reset(env->stick); cpu_timer_reset(env->hstick); env->gregs[1] = 0; // Memory start env->gregs[2] = ram_size; // Memory size env->gregs[3] = 0; // Machine description XXX if (nr_resets++ == 0) { /* Power on reset */ env->pc = s->prom_addr + 0x20ULL; } else { env->pc = s->prom_addr + 0x40ULL; } env->npc = env->pc + 4; }
static void lx_init(const LxBoardDesc *board, ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { #ifdef TARGET_WORDS_BIGENDIAN int be = 1; #else int be = 0; #endif MemoryRegion *system_memory = get_system_memory(); CPUXtensaState *env = NULL; MemoryRegion *ram, *rom, *system_io; DriveInfo *dinfo; pflash_t *flash = NULL; int n; if (!cpu_model) { cpu_model = "dc232b"; } for (n = 0; n < smp_cpus; n++) { env = cpu_init(cpu_model); if (!env) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } env->sregs[PRID] = n; qemu_register_reset(lx60_reset, env); /* Need MMU initialized prior to ELF loading, * so that ELF gets loaded into virtual addresses */ cpu_state_reset(env); } ram = g_malloc(sizeof(*ram)); memory_region_init_ram(ram, "lx60.dram", ram_size); vmstate_register_ram_global(ram); memory_region_add_subregion(system_memory, 0, ram); system_io = g_malloc(sizeof(*system_io)); memory_region_init(system_io, "lx60.io", 224 * 1024 * 1024); memory_region_add_subregion(system_memory, 0xf0000000, system_io); lx60_fpga_init(system_io, 0x0d020000); if (nd_table[0].vlan) { lx60_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, xtensa_get_extint(env, 1), nd_table); } if (!serial_hds[0]) { serial_hds[0] = qemu_chr_new("serial0", "null", NULL); } serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0), 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); dinfo = drive_get(IF_PFLASH, 0, 0); if (dinfo) { flash = pflash_cfi01_register(0xf8000000, NULL, "lx60.io.flash", board->flash_size, dinfo->bdrv, board->flash_sector_size, board->flash_size / board->flash_sector_size, 4, 0x0000, 0x0000, 0x0000, 0x0000, be); if (flash == NULL) { fprintf(stderr, "Unable to mount pflash\n"); exit(1); } } /* Use presence of kernel file name as 'boot from SRAM' switch. */ if (kernel_filename) { rom = g_malloc(sizeof(*rom)); memory_region_init_ram(rom, "lx60.sram", board->sram_size); vmstate_register_ram_global(rom); memory_region_add_subregion(system_memory, 0xfe000000, rom); /* Put kernel bootparameters to the end of that SRAM */ if (kernel_cmdline) { size_t cmdline_size = strlen(kernel_cmdline) + 1; size_t bp_size = sizeof(BpTag[4]) + cmdline_size; uint32_t tagptr = (0xfe000000 + board->sram_size - bp_size) & ~0xff; env->regs[2] = tagptr; tagptr = put_tag(tagptr, 0x7b0b, 0, NULL); if (cmdline_size > 1) { tagptr = put_tag(tagptr, 0x1001, cmdline_size, kernel_cmdline); } tagptr = put_tag(tagptr, 0x7e0b, 0, NULL); } uint64_t elf_entry; uint64_t elf_lowaddr; int success = load_elf(kernel_filename, translate_phys_addr, env, &elf_entry, &elf_lowaddr, NULL, be, ELF_MACHINE, 0); if (success > 0) { env->pc = elf_entry; } } else { if (flash) { MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); memory_region_init_alias(flash_io, "lx60.flash", flash_mr, 0, board->flash_size); memory_region_add_subregion(system_memory, 0xfe000000, flash_io); } } }
static void lx60_reset(void *opaque) { CPUXtensaState *env = opaque; cpu_state_reset(env); }
static void ppc_heathrow_reset(void *opaque) { CPUPPCState *env = opaque; cpu_state_reset(env); }