static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) { SHPCIC *pcic = p; switch(addr) { case 0 ... 0xfc: cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val); break; case 0x1c0: pcic->par = val; break; case 0x1c4: pcic->mbr = val & 0xff000001; break; case 0x1c8: if ((val & 0xfffc0000) != (pcic->iobr & 0xfffc0000)) { cpu_register_physical_memory(pcic->iobr & 0xfffc0000, 0x40000, IO_MEM_UNASSIGNED); pcic->iobr = val & 0xfffc0001; isa_mmio_init(pcic->iobr & 0xfffc0000, 0x40000); } break; case 0x220: pci_data_write(pcic->bus, pcic->par, val, 4); break; } }
static void sh_pci_reg_write (void *p, target_phys_addr_t addr, uint32_t val) { SHPCIC *pcic = p; switch(addr) { case 0 ... 0xfc: cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val); break; case 0x1c0: pcic->par = val; break; case 0x1c4: pcic->mbr = val; break; case 0x1c8: pcic->iobr = val; break; case 0x220: pci_data_write(pcic->bus, pcic->par, val, 4); break; } }