static void crisv32_arbiter_init(void) { static int initialized; if (initialized) return; initialized = 1; /* * CPU caches are always set to active, but with zero * bandwidth allocated. It should be ok to allocate zero * bandwidth for the caches, because DMA for other channels * will supposedly finish, once their programmed amount is * done, and then the caches will get access according to the * "fixed scheme" for unclaimed slots. Though, if for some * use-case somewhere, there's a maximum CPU latency for * e.g. some interrupt, we have to start allocating specific * bandwidth for the CPU caches too. */ active_clients[EXT_REGION][10] = active_clients[EXT_REGION][11] = 1; crisv32_arbiter_config(EXT_REGION, 0); crisv32_arbiter_config(INT_REGION, 0); if (request_irq(MEMARB_INTR_VECT, crisv32_arbiter_irq, IRQF_DISABLED, "arbiter", NULL)) printk(KERN_ERR "Couldn't allocate arbiter IRQ\n"); #ifndef CONFIG_ETRAX_KGDB /* Global watch for writes to kernel text segment. */ crisv32_arbiter_watch(virt_to_phys(&_stext), &_etext - &_stext, arbiter_all_clients, arbiter_all_write, NULL); #endif }
static void crisv32_arbiter_init(void) { static int initialized; if (initialized) return; initialized = 1; /* */ active_clients[EXT_REGION][10] = active_clients[EXT_REGION][11] = 1; crisv32_arbiter_config(EXT_REGION, 0); crisv32_arbiter_config(INT_REGION, 0); if (request_irq(MEMARB_INTR_VECT, crisv32_arbiter_irq, IRQF_DISABLED, "arbiter", NULL)) printk(KERN_ERR "Couldn't allocate arbiter IRQ\n"); #ifndef CONFIG_ETRAX_KGDB /* */ crisv32_arbiter_watch(virt_to_phys(&_stext), &_etext - &_stext, arbiter_all_clients, arbiter_all_write, NULL); #endif }