static int start_video_dma(struct cx8800_dev *dev, struct cx88_dmaqueue *q, struct cx88_buffer *buf) { struct cx88_core *core = dev->core; cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH21], buf->bpl, buf->risc.dma); cx88_set_scale(core, buf->vb.width, buf->vb.height, buf->vb.field); cx_write(MO_COLOR_CTRL, buf->fmt->cxformat | ColorFormatGamma); cx_write(MO_VIDY_GPCNTRL,GP_COUNT_CONTROL_RESET); q->count = 1; cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_VIDINT); cx_set(MO_VID_INTMSK, 0x0f0011); cx_set(VID_CAPTURE_CONTROL,0x06); cx_set(MO_DEV_CNTRL2, (1<<5)); cx_set(MO_VID_DMACNTRL, 0x11); return 0; }
static int cx8800_start_vbi_dma(struct cx8800_dev *dev, struct cx88_dmaqueue *q, struct cx88_buffer *buf) { struct cx88_core *core = dev->core; /* setup fifo + format */ cx88_sram_channel_setup(dev->core, &cx88_sram_channels[SRAM_CH24], buf->vb.width, buf->risc.dma); cx_write(MO_VBOS_CONTROL, ( (1 << 18) | // comb filter delay fixup (1 << 15) | // enable vbi capture (1 << 11) )); /* reset counter */ cx_write(MO_VBI_GPCNTRL, GP_COUNT_CONTROL_RESET); q->count = 1; /* enable irqs */ cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_VIDINT); cx_set(MO_VID_INTMSK, 0x0f0088); /* enable capture */ cx_set(VID_CAPTURE_CONTROL,0x18); /* start dma */ cx_set(MO_DEV_CNTRL2, (1<<5)); cx_set(MO_VID_DMACNTRL, 0x88); return 0; }
static int cx8800_start_vbi_dma(struct cx8800_dev *dev, struct cx88_dmaqueue *q, struct cx88_buffer *buf) { struct cx88_core *core = dev->core; cx88_sram_channel_setup(dev->core, &cx88_sram_channels[SRAM_CH24], buf->vb.width, buf->risc.dma); cx_write(MO_VBOS_CONTROL, ( (1 << 18) | (1 << 15) | (1 << 11) )); cx_write(MO_VBI_GPCNTRL, GP_COUNT_CONTROL_RESET); q->count = 1; cx_set(MO_PCI_INTMSK, core->pci_irqmask | PCI_INT_VIDINT); cx_set(MO_VID_INTMSK, 0x0f0088); cx_set(VID_CAPTURE_CONTROL,0x18); cx_set(MO_DEV_CNTRL2, (1<<5)); cx_set(MO_VID_DMACNTRL, 0x88); return 0; }