/*--------------------------------------------------------------------*/
static void dac_setup(void)
{
/* Enable the DAC clock on APB1 */
rcc_periph_clock_enable(RCC_DAC);
/* Setup the DAC channel 1, with timer 2 as trigger source.
* Assume the DAC has woken up by the time the first transfer occurs */
dac_trigger_enable(CHANNEL_1);
dac_set_trigger_source(DAC_CR_TSEL1_T2);
dac_dma_enable(CHANNEL_1);
dac_enable(CHANNEL_1);
}
/*--------------------------------------------------------------------*/
void dac_setup(void)
{
/* Enable the DAC clock on APB1 */
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_DACEN);
/* Set port PA4 for DAC1 output to 'alternate function'. Output driver mode is irrelevant. */
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO4);
/* Setup the DAC channel 1, with timer 2 as trigger source. Assume the DAC has
woken up by the time the first transfer occurs */
dac_trigger_enable(CHANNEL_1);
dac_set_trigger_source(DAC_CR_TSEL1_T2);
dac_dma_enable(CHANNEL_1);
dac_enable(CHANNEL_1);
}
void funcgen_plat_dac_setup(int channel) {
/* Setup the DAC channel 1, with timer 2 as trigger source.
* Assume the DAC has woken up by the time the first transfer occurs */
int chan;
switch (channel) {
case 1: dac_set_trigger_source(DAC_CR_TSEL2_T7);
chan = CHANNEL_2;
break;
default:
case 0:
dac_set_trigger_source(DAC_CR_TSEL1_T6);
chan = CHANNEL_1;
break;
}
dac_trigger_enable(chan);
dac_dma_enable(chan);
dac_enable(chan);
}
/*--------------------------------------------------------------------*/
void hardware_setup(void)
{
/* Setup the clock to 72MHz from the 8MHz external crystal */
rcc_clock_setup_in_hse_8mhz_out_72mhz();
/* Enable GPIOA, GPIOB and GPIOC clocks.
APB2 (High Speed Advanced Peripheral Bus) peripheral clock enable register (RCC_APB2ENR)
Set RCC_APB2ENR_IOPBEN for port B, RCC_APB2ENR_IOPAEN for port A and RCC_APB2ENR_IOPAEN
for Alternate Function clock */
rcc_periph_clock_enable(RCC_GPIOA);
rcc_periph_clock_enable(RCC_GPIOB);
rcc_periph_clock_enable(RCC_GPIOC);
rcc_periph_clock_enable(RCC_AFIO);
/* Digital Test output PC0 */
gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, GPIO0);
/* ----------------- Timer 2 Interrupt and DAC control*/
/* Enable TIM2 clock. */
rcc_periph_clock_enable(RCC_TIM2);
/* Enable TIM2 interrupt. */
nvic_enable_irq(NVIC_TIM2_IRQ);
timer_reset(TIM2);
/* Timer global mode:
* - No divider
* - Alignment edge
* - Direction up
*/
timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT,
TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP);
/* Continous mode. */
timer_continuous_mode(TIM2);
timer_set_period(TIM2, 1000);
/* Disable outputs. */
timer_disable_oc_output(TIM2, TIM_OC1 | TIM_OC2 | TIM_OC3 | TIM_OC4);
/* Configure global mode of output channel 1, disabling the output. */
timer_disable_oc_clear(TIM2, TIM_OC1);
timer_disable_oc_preload(TIM2, TIM_OC1);
timer_set_oc_slow_mode(TIM2, TIM_OC1);
timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_FROZEN);
/* Set the capture compare value for OC1. */
timer_set_oc_value(TIM2, TIM_OC1, 1000);
/* ARR reload disable. */
timer_disable_preload(TIM2);
/* Counter enable. */
timer_enable_counter(TIM2);
/* Enable commutation interrupt. */
timer_enable_irq(TIM2, TIM_DIER_CC1IE);
/* Set port PA4 for DAC1 to 'alternate function'. Output driver mode is ignored. */
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO4);
/* Enable the DAC clock on APB1 */
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_DACEN);
/* Setup the DAC, software trigger source. Assume the DAC has
woken up by the time the first interrupt occurs */
dac_trigger_enable(CHANNEL_D);
dac_set_trigger_source(DAC_CR_TSEL1_SW | DAC_CR_TSEL2_SW);
dac_enable(CHANNEL_D);
dac_load_data_buffer_dual(0, 0, RIGHT8);
}
