static int gen_auto_negotiate(int phy_addr)
{
u_int16_t tmp;
u_int16_t val;
unsigned long cntr = 0;
if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
return 0;
val = tmp | BMCR_FULLDPLX | BMCR_ANENABLE |
BMCR_SPEED100;
davinci_eth_phy_write(phy_addr, MII_BMCR, val);
if (!davinci_eth_phy_read(phy_addr, MII_ADVERTISE, &val))
return 0;
val |= (ADVERTISE_100FULL | ADVERTISE_100HALF | ADVERTISE_10FULL |
ADVERTISE_10HALF);
davinci_eth_phy_write(phy_addr, MII_ADVERTISE, val);
if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
return(0);
#ifdef DAVINCI_EMAC_GIG_ENABLE
davinci_eth_phy_read(phy_addr, MII_CTRL1000, &val);
val |= PHY_1000BTCR_1000FD;
val &= ~PHY_1000BTCR_1000HD;
davinci_eth_phy_write(phy_addr, MII_CTRL1000, val);
davinci_eth_phy_read(phy_addr, MII_CTRL1000, &val);
#endif
/* Restart Auto_negotiation */
tmp |= BMCR_ANRESTART;
davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
/*check AutoNegotiate complete */
do {
udelay(40000);
if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
return 0;
if (tmp & BMSR_ANEGCOMPLETE)
break;
cntr++;
} while (cntr < 200);
if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
return(0);
if (!(tmp & BMSR_ANEGCOMPLETE))
return(0);
return(gen_get_link_speed(phy_addr));
}
int lxt972_get_link_speed(int phy_addr)
{
u_int16_t stat1, tmp;
volatile emac_regs *emac = (emac_regs *)EMAC_BASE_ADDR;
if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1))
return(0);
if (!(stat1 & PHY_LXT971_STAT2_LINK)) /* link up? */
return(0);
if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
return(0);
tmp |= PHY_LXT971_DIG_CFG_MII_DRIVE;
davinci_eth_phy_write(phy_addr, PHY_LXT971_DIG_CFG, tmp);
/* Read back */
if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp))
return(0);
/* Speed doesn't matter, there is no setting for it in EMAC... */
if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
/* set DM644x EMAC for Full Duplex */
emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
} else {
/*set DM644x EMAC for Half Duplex */
emac->MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
}
return(1);
}
static int gen_auto_negotiate(int phy_addr)
{
u_int16_t tmp;
u_int16_t val;
unsigned int cntr = 0;
if (!davinci_eth_phy_read(phy_addr, PHY_BMCR, &tmp))
return(0);
val = tmp | PHY_BMCR_DPLX | PHY_BMCR_AUTON
| PHY_BMCR_100MB ;
davinci_eth_phy_write(phy_addr, PHY_BMCR, val);
davinci_eth_phy_read(phy_addr, PHY_BMCR, &val);
/* advertise 100 Full Duplex */
davinci_eth_phy_read(phy_addr,PHY_ANAR, &val);
val |= (PHY_ANLPAR_10 | PHY_ANLPAR_10FD | PHY_ANLPAR_TX
| PHY_ANLPAR_TXFD);
davinci_eth_phy_write(phy_addr,PHY_ANAR, val);
davinci_eth_phy_read(phy_addr,PHY_ANAR, &val);
davinci_eth_phy_read(phy_addr, PHY_BMCR, &tmp);
/* Restart Auto_negotiation */
tmp |= PHY_BMCR_AUTON;
davinci_eth_phy_write(phy_addr, PHY_BMCR, tmp);
/*check AutoNegotiate complete - it can take upto 3 secs*/
do{
udelay(40000);
cntr++;
if (davinci_eth_phy_read(phy_addr, PHY_BMSR, &tmp)){
if(tmp & PHY_BMSR_AUTN_COMP)
break;
}
}while(cntr < 250);
if (!davinci_eth_phy_read(phy_addr, PHY_BMSR, &tmp))
return(0);
if (!(tmp & PHY_BMSR_AUTN_COMP))
return(0);
return(gen_get_link_speed(phy_addr));
}
int dp83848_auto_negotiate(int phy_addr)
{
u_int16_t tmp;
if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
return(0);
/* Restart Auto_negotiation */
tmp &= ~DP83848_AUTONEG; /* remove autonegotiation enable */
tmp |= DP83848_ISOLATE; /* Electrically isolate PHY */
davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
/* Set the Auto_negotiation Advertisement Register
* MII advertising for Next page, 100BaseTxFD and HD,
* 10BaseTFD and HD, IEEE 802.3
*/
tmp = DP83848_NP | DP83848_TX_FDX | DP83848_TX_HDX |
DP83848_10_FDX | DP83848_10_HDX | DP83848_AN_IEEE_802_3;
davinci_eth_phy_write(phy_addr, DP83848_ANA_REG, tmp);
/* Read Control Register */
if (!davinci_eth_phy_read(phy_addr, DP83848_CTL_REG, &tmp))
return(0);
tmp |= DP83848_SPEED_SELECT | DP83848_AUTONEG | DP83848_DUPLEX_MODE;
davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
/* Restart Auto_negotiation */
tmp |= DP83848_RESTART_AUTONEG;
davinci_eth_phy_write(phy_addr, DP83848_CTL_REG, tmp);
/*check AutoNegotiate complete */
udelay(10000);
if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp))
return(0);
if (!(tmp & DP83848_AUTONEG_COMP))
return(0);
return (dp83848_get_link_speed(phy_addr));
}
int lxt972_init_phy(int phy_addr)
{
int ret = 1;
if (!lxt972_get_link_speed(phy_addr)) {
/* Try another time */
ret = lxt972_get_link_speed(phy_addr);
}
/* Disable PHY Interrupts */
davinci_eth_phy_write(phy_addr, PHY_LXT971_INT_ENABLE, 0);
return(ret);
}
int dp83848_init_phy(int phy_addr)
{
int ret = 1;
if (!dp83848_get_link_speed(phy_addr)) {
/* Try another time */
udelay(100000);
ret = dp83848_get_link_speed(phy_addr);
}
/* Disable PHY Interrupts */
davinci_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0);
return(ret);
}
int lxt972_auto_negotiate(int phy_addr)
{
u_int16_t tmp;
if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp))
return(0);
/* Restart Auto_negotiation */
tmp |= BMCR_ANRESTART;
davinci_eth_phy_write(phy_addr, MII_BMCR, tmp);
/*check AutoNegotiate complete */
udelay (10000);
if (!davinci_eth_phy_read(phy_addr, MII_BMSR, &tmp))
return(0);
if (!(tmp & BMSR_ANEGCOMPLETE))
return(0);
return (lxt972_get_link_speed(phy_addr));
}
static int gen_auto_negotiate(int phy_addr)
{
u_int16_t tmp;
if (!davinci_eth_phy_read(phy_addr, PHY_BMCR, &tmp))
return(0);
/* Restart Auto_negotiation */
tmp |= PHY_BMCR_AUTON;
davinci_eth_phy_write(phy_addr, PHY_BMCR, tmp);
/*check AutoNegotiate complete */
udelay (10000);
if (!davinci_eth_phy_read(phy_addr, PHY_BMSR, &tmp))
return(0);
if (!(tmp & PHY_BMSR_AUTN_COMP))
return(0);
return(gen_get_link_speed(phy_addr));
}
/*
* This function initializes the emac hardware. It does NOT initialize
* EMAC modules power or pin multiplexors, that is done by board_init()
* much earlier in bootup process. Returns 1 on success, 0 otherwise.
*/
int davinci_emac_initialize(void)
{
u_int32_t phy_id;
u_int16_t tmp;
int i;
int ret;
struct eth_device *dev;
dev = malloc(sizeof *dev);
if (dev == NULL)
return -1;
memset(dev, 0, sizeof *dev);
strcpy(dev->name, "DaVinci-EMAC");
dev->iobase = 0;
dev->init = davinci_eth_open;
dev->halt = davinci_eth_close;
dev->send = davinci_eth_send_packet;
dev->recv = davinci_eth_rcv_packet;
dev->write_hwaddr = davinci_eth_set_mac_addr;
eth_register(dev);
davinci_eth_mdio_enable();
/* let the EMAC detect the PHYs */
udelay(5000);
for (i = 0; i < 256; i++) {
if (readl(&adap_mdio->ALIVE))
break;
udelay(1000);
}
if (i >= 256) {
printf("No ETH PHY detected!!!\n");
return(0);
}
/* Find if PHY(s) is/are connected */
ret = davinci_eth_phy_detect();
if (!ret)
return(0);
else
debug_emac(" %d ETH PHY detected\n", ret);
/* Get PHY ID and initialize phy_ops for a detected PHY */
for (i = 0; i < num_phy; i++) {
if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID1,
&tmp)) {
active_phy_addr[i] = 0xff;
continue;
}
phy_id = (tmp << 16) & 0xffff0000;
if (!davinci_eth_phy_read(active_phy_addr[i], MII_PHYSID2,
&tmp)) {
active_phy_addr[i] = 0xff;
continue;
}
phy_id |= tmp & 0x0000ffff;
switch (phy_id) {
#ifdef PHY_KSZ8873
case PHY_KSZ8873:
sprintf(phy[i].name, "KSZ8873 @ 0x%02x",
active_phy_addr[i]);
phy[i].init = ksz8873_init_phy;
phy[i].is_phy_connected = ksz8873_is_phy_connected;
phy[i].get_link_speed = ksz8873_get_link_speed;
phy[i].auto_negotiate = ksz8873_auto_negotiate;
break;
#endif
#ifdef PHY_LXT972
case PHY_LXT972:
sprintf(phy[i].name, "LXT972 @ 0x%02x",
active_phy_addr[i]);
phy[i].init = lxt972_init_phy;
phy[i].is_phy_connected = lxt972_is_phy_connected;
phy[i].get_link_speed = lxt972_get_link_speed;
phy[i].auto_negotiate = lxt972_auto_negotiate;
break;
#endif
#ifdef PHY_DP83848
case PHY_DP83848:
sprintf(phy[i].name, "DP83848 @ 0x%02x",
active_phy_addr[i]);
phy[i].init = dp83848_init_phy;
phy[i].is_phy_connected = dp83848_is_phy_connected;
phy[i].get_link_speed = dp83848_get_link_speed;
phy[i].auto_negotiate = dp83848_auto_negotiate;
break;
#endif
#ifdef PHY_ET1011C
case PHY_ET1011C:
sprintf(phy[i].name, "ET1011C @ 0x%02x",
active_phy_addr[i]);
phy[i].init = gen_init_phy;
phy[i].is_phy_connected = gen_is_phy_connected;
phy[i].get_link_speed = et1011c_get_link_speed;
phy[i].auto_negotiate = gen_auto_negotiate;
break;
#endif
default:
sprintf(phy[i].name, "GENERIC @ 0x%02x",
active_phy_addr[i]);
phy[i].init = gen_init_phy;
phy[i].is_phy_connected = gen_is_phy_connected;
phy[i].get_link_speed = gen_get_link_speed;
phy[i].auto_negotiate = gen_auto_negotiate;
}
debug("Ethernet PHY: %s\n", phy[i].name);
int retval;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN);
mdiodev->read = davinci_mii_phy_read;
mdiodev->write = davinci_mii_phy_write;
retval = mdio_register(mdiodev);
if (retval < 0)
return retval;
#ifdef DAVINCI_EMAC_GIG_ENABLE
#define PHY_CONF_REG 22
/* Enable PHY to clock out TX_CLK */
davinci_eth_phy_read(active_phy_addr[i], PHY_CONF_REG, &tmp);
tmp |= PHY_CONF_TXCLKEN;
davinci_eth_phy_write(active_phy_addr[i], PHY_CONF_REG, tmp);
davinci_eth_phy_read(active_phy_addr[i], PHY_CONF_REG, &tmp);
#endif
}
#if defined(CONFIG_TI816X) || (defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \
defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \
!defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE))
for (i = 0; i < num_phy; i++) {
if (phy[i].is_phy_connected(i))
phy[i].auto_negotiate(i);
}
#endif
return(1);
}
static int davinci_mii_phy_write(struct mii_dev *bus, int addr, int devad,
int reg, u16 value)
{
return davinci_eth_phy_write(addr, reg, value) ? 0 : 1;
}
static int davinci_mii_phy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value)
{
return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1);
}
