void enable_caches(void) { /* Enable D-cache. I-cache is already enabled in start.S */ #ifdef CONFIG_SPL dcache_enable(); #endif }
uint32_t cpudep_ap_bootstrap() { uint32_t msr, sp, csr; /* Enable L1 caches */ csr = mfspr(SPR_L1CSR0); if ((csr & L1CSR0_DCE) == 0) { dcache_inval(); dcache_enable(); } csr = mfspr(SPR_L1CSR1); if ((csr & L1CSR1_ICE) == 0) { icache_inval(); icache_enable(); } /* Set MSR */ msr = PSL_ME; mtmsr(msr); /* Assign pcpu fields, return ptr to this AP's idle thread kstack */ pcpup->pc_curthread = pcpup->pc_idlethread; pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb; sp = pcpup->pc_curpcb->pcb_sp; /* XXX shouldn't the pcb_sp be checked/forced for alignment here?? */ return (sp); }
void start_armboot(void) { ENTRY entry = (ENTRY)IMAGE_ENTRY; unsigned char *pdst = (unsigned char *)IMAGE_ENTRY; unsigned int image_data_len = input_data_end - input_data; malloc_start = (char *)(_armboot_start - CONFIG_SYS_MALLOC_LEN); uart_early_puts("\r\n\r\nCompressed-boot v1.0.0\r\n"); /* DDR should larger than 16M */ mmu_init((MEM_BASE_DDR + 0x4000), MEM_BASE_DDR, 0x1000000); dcache_enable(0); if (input_data[0] == 0x5D) { uart_early_puts("Uncompress"); decompress(input_data, image_data_len, pdst); uart_early_puts("Ok\r\n"); } else { int *s = (int *)input_data; int *d = (int *)pdst; unsigned int len = ((image_data_len + 3) >> 2); while (len--) *d++ = *s++; } dcache_disable(); entry(); }
unsigned long do_bootelf_exec(ulong (*entry)(int, char * const[]), int argc, char * const argv[]) { unsigned long ret; int i; /* * QNX images require the data cache is disabled. * Data cache is already flushed, so just turn it off. */ int dcache = dcache_status(); if (dcache) dcache_disable(); /* * pass address parameter as argv[0] (aka command name), * and all remaining args */ for(i=0;i<argc;i++) { printf("%d : %s\n",argc,argv); } ret = entry(argc, argv); if (dcache) dcache_enable(); return ret; }
int do_dcache ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { switch (argc) { case 2: /* on / off */ switch (on_off(argv[1])) { #if 0 /* prevented by varargs handling; FALLTROUGH is harmless, too */ default: printf ("Usage:\n%s\n", cmdtp->usage); return; #endif case 0: dcache_disable(); break; case 1: dcache_enable (); break; } /* FALL TROUGH */ case 1: /* get status */ printf ("Data (writethrough) Cache is %s\n", dcache_status() ? "ON" : "OFF"); return 0; default: printf ("Usage:\n%s\n", cmdtp->usage); return 1; } return 0; }
void enable_caches(void) { icache_enable(); #ifndef CONFIG_SYS_DCACHE_OFF dcache_enable(); #endif }
int board_init(void) { DECLARE_GLOBAL_DATA_PTR; u32 reg; dm9000_pre_init(); /* set GPIO for Display Controller */ reg = readl(MIFPCON); reg &= ~(1 << 3); writel(reg, MIFPCON); reg = readl(SPCON); reg &= ~(3 << 0); writel(reg | 0x1, SPCON); writel(0xaaaaaaaa, GPICON); writel(0xaaaaaa, GPJCON); gd->bd->bi_arch_number = MACH_TYPE; gd->bd->bi_boot_params = (PHYS_SDRAM_1+0x100); #if 0 icache_enable(); dcache_enable(); #endif return 0; }
int board_init(void) { struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; icache_enable(); #ifdef USE_920T_MMU dcache_enable(); #endif /* * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of * 14.7456/2 MHz */ uint32_t value = readl(&syscon->pwrcnt); value |= SYSCON_PWRCNT_UART_BAUD; writel(value, &syscon->pwrcnt); /* Enable the uart in devicecfg */ value = readl(&syscon->devicecfg); value |= 1<<18 /* U1EN */; writel(0xAA, &syscon->sysswlock); writel(value, &syscon->devicecfg); /* Machine number, as defined in linux/arch/arm/tools/mach-types */ gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* adress of boot parameters */ gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; /* We have a console */ gd->have_console = 1; return 0; }
int board_mmc_init(bd_t *bis) { int err; struct davinci_gpio *gpio23_base = (struct davinci_gpio *)DAVINCI_GPIO_BANK23; /* GIO42 (~eMMC_RESET) pinmux setting */ writel((readl(PINMUX4) & 0x3FFFFFFF), PINMUX4); /* set GIO42 (~eMMC_RESET) output */ writel((readl(&gpio23_base->dir) & ~(1 << 10)), &gpio23_base->dir); /* GIO42 (~eMMC_RESET) output High */ writel((readl(&gpio23_base->set_data) | (1 << 10)), &gpio23_base->set_data); /* * enabling cache make mmc read faster * but tftp doesn't work */ icache_enable (); dcache_enable (); /* Add slot-0 to mmc subsystem */ err = davinci_mmc_init(bis, &mmc_sd0); if (err) return err; return err; }
void enable_caches(void) { #ifndef CONFIG_SYS_DCACHE_OFF /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); #endif }
/* * Some of these functions are needed purely because the functions they * call return void. If we change them to return 0, these stubs can go away. */ static int initr_caches(void) { /* Enable caches */ //enable_caches(); dcache_enable(); return 0; }
//============================================================== int l1cache_post_test(int flags) { int i; unsigned result, pattern=0; int status; status = dcache_status(); if(dcache_status() == OFF) dcache_enable(); dcache_flush(); icache_invalid(); dcache_clean(); dcache_disable(); // must invalid dcache after dcache_disable // if no valid dcache, dcache_enable() will jump here dcache_invalid(); asm("mov r0, r0"); asm("mov r0, r0"); asm("mov r0, r0"); for(i=0; i<ARRAY_SIZE(L1_cache_pattern); i++){ result = test_w_l1cache(0x55555555, L1_cache_pattern[i]); if(result != 0){ pattern = L1_cache_pattern[i]; break; } result = test_w_l1cache(0x55555555, ~L1_cache_pattern[i]); if(result != 0){ pattern = ~L1_cache_pattern[i]; break; } } if(status == ON) dcache_enable(); if(i<ARRAY_SIZE(L1_cache_pattern)){ post_log("<%d>%s:%d: l1cache: test fail: Error address=0x%x, pattern=0x%x\n", SYSTEST_INFO_L2, __FUNCTION__, __LINE__, result, pattern); return -1; } else{ post_log("<%d>l1cache test pattern count=%d\n", SYSTEST_INFO_L2, ARRAY_SIZE(L1_cache_pattern)); return 0; } }
int board_init (void) { S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); clk_power->CLKDIVN = S3C2410_CLKDIV; /* change to asynchronous bus mod */ __asm__( "mrc p15, 0, r1, c1, c0, 0\n" /* read ctrl register */ "orr r1, r1, #0xc0000000\n" /* Asynchronous */ "mcr p15, 0, r1, c1, c0, 0\n" /* write ctrl register */ :::"r1" ); /* to reduce PLL lock time, adjust the LOCKTIME register */ clk_power->LOCKTIME = 0xFFFFFF; /* configure MPLL */ clk_power->MPLLCON = S3C2410_MPLL_200MHZ; /* some delay between MPLL and UPLL */ delay (4000); /* configure UPLL */ clk_power->UPLLCON = S3C2410_UPLL_48MHZ; /* some delay between MPLL and UPLL */ delay (8000); /* set up the I/O ports */ gpio->GPACON = 0x007FFFFF; gpio->GPBCON = 0x00045555; gpio->GPBDAT &= (~(1<<6)); gpio->GPBUP = 0x000007FF; gpio->GPCCON = 0xAAAAAAAA; gpio->GPCUP = 0x0000FFFF; gpio->GPDCON = 0xAAAAAAAA; gpio->GPDUP = 0x0000FFFF; gpio->GPECON = 0xAAAAAAAA; gpio->GPEUP = 0x0000FFFF; gpio->GPFCON = 0x000055AA; gpio->GPFUP = 0x000000FF; gpio->GPGCON = 0xFF95FFBA; gpio->GPGUP = 0x0000FFFF; gpio->GPHCON = 0x002AFAAA; gpio->GPHUP = 0x000007FF; /* arch number of SMDK2410-Board */ gd->bd->bi_arch_number = MACH_TYPE_SMDK2410; /* adress of boot parameters */ gd->bd->bi_boot_params = 0x30000100; icache_enable(); dcache_enable(); return 0; }
int board_init (void) { S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); /* to reduce PLL lock time, adjust the LOCKTIME register */ clk_power->LOCKTIME = 0xFFFFFF; /* FCLK:HCLK:PCLK = 1:4:8 */ clk_power->CLKDIVN = 0x05; /* Change to Asynchronous bus mode */ __asm__( "mrc p15, 0, r1, c1, c0, 0\n" /* read ctrl register */ "orr r1, r1, #0xc0000000\n" /* Asynchronous */ "mcr p15, 0, r1, c1, c0, 0\n" /* write ctrl register */ :::"r1" ); /* configure MPLL */ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); /* some delay between MPLL and UPLL */ delay (4000); /* configure UPLL */ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); /* some delay between MPLL and UPLL */ delay (8000); /* set up the I/O ports */ gpio->GPACON = 0x007FFFFF; gpio->GPBCON = 0x00044554; gpio->GPBUP = 0x000007FF; gpio->GPCCON = 0xAAAAAAAA; gpio->GPCUP = 0x0000FFFF; gpio->GPDCON = 0xAAAAAAAA; gpio->GPDUP = 0x0000FFFF; gpio->GPECON = 0xAAAAAAAA; gpio->GPEUP = 0x0000FFFF; gpio->GPFCON = 0x000055AA; gpio->GPFUP = 0x000000FF; gpio->GPGCON = 0xFF95FFBA; gpio->GPGUP = 0x0000FFFF; gpio->GPHCON = 0x002AFAAA; gpio->GPHUP = 0x000007FF; /* arch number of SMDK2410-Board */ gd->bd->bi_arch_number = MACH_TYPE_MINI2440; /* adress of boot parameters */ gd->bd->bi_boot_params = 0x30000100; icache_enable(); dcache_enable(); return 0; }
static unsigned long efi_run_in_el2(ulong (*entry)(void *image_handle, struct efi_system_table *st), void *image_handle, struct efi_system_table *st) { /* Enable caches again */ dcache_enable(); return entry(image_handle, st); }
int board_init (void) { DECLARE_GLOBAL_DATA_PTR; volatile unsigned int tmp; mc9328sid = SIDR; GPCR = 0x000003AB; /* I/O pad driving strength */ /* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */ /* MX1_CS1L = 0x11110601; */ MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */ /* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and * BCLK divider to 2 (i.e. BCLK to 48 MHz) */ CSCR = 0xAF000403; CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */ CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */ /* setup cs4 for cs8900 ethernet */ CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */ CS4L = 0x00001501; GIUS(0) &= 0xFF3FFFFF; GPR(0) &= 0xFF3FFFFF; tmp = *(unsigned int *)(0x1500000C); tmp = *(unsigned int *)(0x1500000C); SetAsynchMode(); gd->bd->bi_arch_number = MACH_TYPE_MX1ADS; gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */ icache_enable(); dcache_enable(); /* set PERCLKs */ PCDR = 0x00000055; /* set PERCLKS */ /* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place * all sources selected as normal interrupt */ /* MX1_INTTYPEH = 0; MX1_INTTYPEL = 0; */ return 0; }
/* * Miscellaneous platform dependent initialisations */ int board_init (void) { S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); /* set up the I/O ports */ /* gpio->GPACON = 0x007FFFFF; gpio->GPBCON = 0x00055555; gpio->GPBUP = 0x000007FF; gpio->GPCCON = 0xAAAAAAAA; gpio->GPCUP = 0x0000FFFF; gpio->GPDCON = 0xAAAAAAAA; gpio->GPDUP = 0x0000FFFF; gpio->GPECON = 0xAAAAAAAA; gpio->GPEUP = 0x0000FFFF; gpio->GPFCON = 0x000055AA; gpio->GPFUP = 0x000000FF; gpio->GPGCON = 0xFF94FFBA; gpio->GPGUP = 0x0000FFEF; gpio->GPGDAT = gpio->GPGDAT & ((~(1<<4)) | (1<<4)) ; gpio->GPHCON = 0x002AFAAA; gpio->GPHUP = 0x000007FF; gpio->GPJCON = 0x02aaaaaa; gpio->GPJUP = 0x00001fff; */ gpio->GPACON = 0x007FFFFF; //每个 pin的设置取决于原理图,从原理图可知 GPA的每个IO都是使用的其特殊功能 gpio->GPBCON = 0x00044555; //每组GPIO的配置方式不一致,需要结合主控的数据手册和板子的原理图来进行配置 gpio->GPBUP = 0x000007FF; gpio->GPCCON = 0xAAAAAAAA; gpio->GPCUP = 0x0000FFFF; gpio->GPDCON = 0xAAAAAAAA; gpio->GPDUP = 0x0000FFFF; gpio->GPECON = 0xAAAAAAAA; gpio->GPEUP = 0x0000FFFF; gpio->GPFCON = 0x000055AA; gpio->GPFUP = 0x000000FF; gpio->GPGCON = 0xFF95FFBA; gpio->GPGUP = 0x0000FFFF; gpio->GPHCON = 0x002AFAAA; gpio->GPHUP = 0x000007FF; // S3C24X0_I2S * const i2s = S3C24X0_GetBase_I2S(); //HJ_add 屏蔽IIS, // i2s->IISCON = 0x00; //HJ_add 屏蔽IIS, /* arch number of TQ2440-Board */ gd->bd->bi_arch_number = MACH_TYPE_JZ2440; /* adress of boot parameters */ gd->bd->bi_boot_params = 0x30000100; icache_enable(); dcache_enable(); return 0; }
void kgdb_flush_cache_all(void) { if (dcache_status()) { dcache_disable(); dcache_enable(); } if (icache_status()) { icache_disable(); icache_enable(); } }
//============================================================== unsigned test_w_l1cache(unsigned fill_value, unsigned modify_value) { unsigned *addr; unsigned size, err_addr, val; int i; // current dcache is disable // clear no-cache memory block addr = (unsigned*)no_cache_mem_start; size = (cache_size)/sizeof(unsigned); for(i=0; i<size; i++, addr++) *addr = fill_value; // asm("dmb"); // asm("isb"); // map cache-memory data to cache addr = (unsigned*)cache_mem_start; size = cache_size/CONFIG_SYS_CACHE_LINE_SIZE; dcache_enable(); // asm("dmb"); // asm("isb"); for(i=0; i<size; i++, addr+=CONFIG_SYS_CACHE_LINE_SIZE) val = *addr; // write to cache addr = (unsigned*)cache_mem_start; size = cache_size/sizeof(unsigned); for(i=0; i<size; i++, addr++){ *addr = modify_value; } dcache_flush(); dcache_clean(); dcache_disable(); dcache_invalid(); asm("mov r0, r0"); asm("mov r0, r0"); asm("mov r0, r0"); err_addr = 0; addr = (unsigned*)no_cache_mem_start; for(i=0; i<size; i++, addr++){ if(*addr != modify_value){ err_addr = (unsigned)addr; break; } } return err_addr; }
int jpeg_decode(void) { enable_mmu(); dcache_enable(); printf("mmu_enable\n"); LoadJpegFile((void *)VIDEO_DATA_BASE); dcache_disable(); stop_mmu(); return 0; }
int board_init(void) { /* arch number of MINI2440-Board */ gd->bd->bi_arch_number = MACH_TYPE_MINI2440; /* adress of boot parameters */ gd->bd->bi_boot_params = 0x30000100; icache_enable(); dcache_enable(); return 0; }
int board_init (void) { struct s3c24x0_clock_power * const clk_power = s3c24x0_get_base_clock_power(); struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); /* to reduce PLL lock time, adjust the LOCKTIME register */ clk_power->LOCKTIME = 0xFFFFFF; /* configure MPLL */ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); /* some delay between MPLL and UPLL */ delay (4000); /* configure UPLL */ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); /* some delay between MPLL and UPLL */ delay (8000); /* set up the I/O ports */ gpio->GPACON = 0x007FFFFF; gpio->GPBCON = 0x00044555; gpio->GPBUP = 0x000007FF; gpio->GPCCON = 0xAAAAAAAA; gpio->GPCUP = 0x0000FFFF; gpio->GPDCON = 0xAAAAAAAA; gpio->GPDUP = 0x0000FFFF; gpio->GPECON = 0xAAAAAAAA; gpio->GPEUP = 0x0000FFFF; gpio->GPFCON = 0x000055AA; gpio->GPFUP = 0x000000FF; gpio->GPGCON = 0xFD95FFBA; gpio->GPGUP = 0x0000EFFF; gpio->GPGDAT &= ~(1<<12); gpio->GPHCON = 0x002AFAAA; gpio->GPHUP = 0x000007FF; /* arch number of S3C2440-Board */ gd->bd->bi_arch_number = MACH_TYPE_SMDK2440A; /* adress of boot parameters */ gd->bd->bi_boot_params = 0x30000100; icache_enable(); dcache_enable(); return 0; }
int board_init (void) { DECLARE_GLOBAL_DATA_PTR; S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); /* to reduce PLL lock time, adjust the LOCKTIME register */ clk_power->LOCKTIME = 0xFFFFFF; /* configure MPLL */ clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); /* some delay between MPLL and UPLL */ delay (4000); /* configure UPLL */ clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); /* some delay between MPLL and UPLL */ delay (8000); /* set up the I/O ports */ gpio->GPACON = 0x007FFFFF; gpio->GPBCON = 0x00044555; gpio->GPBUP = 0x000007FF; gpio->GPCCON = 0xAAAAAAAA; gpio->GPCUP = 0x0000FFFF; gpio->GPDCON = 0xAAAAAAAA; gpio->GPDUP = 0x0000FFFF; gpio->GPECON = 0xAAAAAAAA; gpio->GPEUP = 0x0000FFFF; gpio->GPFCON = 0x000055AA; gpio->GPFUP = 0x000000FF; gpio->GPGCON = 0xFF95FFBA; gpio->GPGUP = 0x0000FFFF; gpio->GPHCON = 0x002AFAAA; gpio->GPHUP = 0x000007FF; /* arch number of SMDK2410-Board */ gd->bd->bi_arch_number = MACH_TYPE_SMDK2410; /* adress of boot parameters */ gd->bd->bi_boot_params = 0x30000100; icache_enable(); dcache_enable(); return 0; }
int board_init(void) { DECLARE_GLOBAL_DATA_PTR; smc9115_pre_init(); gd->bd->bi_arch_number = MACH_TYPE; gd->bd->bi_boot_params = (PHYS_SDRAM_1+0x100); #if 0 icache_enable(); dcache_enable(); #endif return 0; }
int board_early_init_f(void) { mc9328sid = SIDR; GPCR = 0x000003AB; /* I/O pad driving strength */ /* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */ /* MX1_CS1L = 0x11110601; */ MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */ /* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and * BCLK divider to 2 (i.e. BCLK to 48 MHz) */ CSCR = 0xAF000403; CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */ CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */ /* setup cs4 for cs8900 ethernet */ CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */ CS4L = 0x00001501; GIUS (0) &= 0xFF3FFFFF; GPR (0) &= 0xFF3FFFFF; readl(0x1500000C); readl(0x1500000C); SetAsynchMode (); icache_enable (); dcache_enable (); /* set PERCLKs */ PCDR = 0x00000055; /* set PERCLKS */ /* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes * PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place * all sources selected as normal interrupt */ /* MX1_INTTYPEH = 0; MX1_INTTYPEL = 0; */ return 0; }
/* * Miscellaneous platform dependent initialisations */ int board_init(void) { struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *) MB86R0x_CCNT_BASE; /* We select mode 0 for group 2 and mode 1 for group 4 */ writel(0x00000010, &ccnt->cmux_md); gd->flags = 0; gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000; icache_enable(); dcache_enable(); return 0; }
int board_init(void) { DECLARE_GLOBAL_DATA_PTR; cs8900_pre_init(); usb_pre_init(); // SMBCR4_REG = 0x00000015; // SMBCR1_REG = 0x00000015; gd->bd->bi_arch_number = MACH_TYPE; gd->bd->bi_boot_params = (PHYS_SDRAM_1+0x100); #if 0 icache_enable(); dcache_enable(); #endif return 0; }
void enable_caches(void) { #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) enum dcache_option option = DCACHE_WRITETHROUGH; #else enum dcache_option option = DCACHE_WRITEBACK; #endif /* Avoid random hang when download by usb */ invalidate_dcache_all(); /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); /* Enable caching on OCRAM and ROM */ mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR, ROMCP_ARB_END_ADDR, option); mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option); }
int misc_init_r(void) { #if defined(CONFIG_CMD_NET) uchar mac_id[6]; if (!eth_getenv_enetaddr("ethaddr", mac_id) && !i2c_read_mac(mac_id)) eth_setenv_enetaddr("ethaddr", mac_id); #endif setenv("verify", "n"); #if defined(CONFIG_SPEAR_USBTTY) setenv("stdin", "usbtty"); setenv("stdout", "usbtty"); setenv("stderr", "usbtty"); #ifndef CONFIG_SYS_NO_DCACHE dcache_enable(); #endif #endif return 0; }
void enable_caches(void) { icache_enable(); dcache_enable(); }