/***********************************************************************
*
* Function: c_entry
*
* Purpose: Application entry point from the startup code
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: Nothing
*
* Notes: None
*
**********************************************************************/
void c_entry(void) {
UNS_8 *p8;
INT_32 toread, idx;
PFV execa = (PFV) STAGE1_LOAD_ADDR;
/* Force SSP configuration, use GPIO_05 (SSP0_CS) in software
control mode */
GPIO->p2_dir_set = P2_DIR_GPIO(5);
GPIO->p2_mux_clr = P2_GPIO05_SSEL0;
GPIO->p_mux_set = P_SPI1CLK_SCK0 | P_SPI1DATAIN_SSP0_MISO |
P_SPI1DATAIO_SSP0_MOSI;
board_spi_config();
/* Read data into memory */
toread = STAGE1_LOAD_SIZE;
p8 = (UNS_8 *) STAGE1_LOAD_ADDR;
idx = SPI_S1APP_OFFSET;
while (toread > 0)
{
*p8 = board_spi_read(idx);
p8++;
idx++;
toread--;
}
#ifdef USE_MMU
dcache_flush();
dcache_inval();
icache_inval();
#endif
execa();
}
uint32_t
cpudep_ap_bootstrap()
{
uint32_t msr, sp, csr;
/* Enable L1 caches */
csr = mfspr(SPR_L1CSR0);
if ((csr & L1CSR0_DCE) == 0) {
dcache_inval();
dcache_enable();
}
csr = mfspr(SPR_L1CSR1);
if ((csr & L1CSR1_ICE) == 0) {
icache_inval();
icache_enable();
}
/* Set MSR */
msr = PSL_ME;
mtmsr(msr);
/* Assign pcpu fields, return ptr to this AP's idle thread kstack */
pcpup->pc_curthread = pcpup->pc_idlethread;
pcpup->pc_curpcb = pcpup->pc_curthread->td_pcb;
sp = pcpup->pc_curpcb->pcb_sp;
/* XXX shouldn't the pcb_sp be checked/forced for alignment here?? */
return (sp);
}
/***********************************************************************
*
* Function: c_entry
*
* Purpose: Application entry point from the startup code
*
* Processing:
* See function.
*
* Parameters: None
*
* Outputs: None
*
* Returns: Nothing
*
* Notes: None
*
**********************************************************************/
void c_entry(void) {
UNS_8 *p8, ret;
INT_32 toread, idx, blk, page, sector;
PFV execa = (PFV) STAGE1_LOAD_ADDR;
/* Initialize NAND FLASH */
if (nand_sb_slc_init() != 1)
{
while (1);
}
/* Read data into memory */
toread = STAGE1_LOAD_SIZE;
blk = 1;
page = 0;
p8 = (UNS_8 *) STAGE1_LOAD_ADDR;
while (toread > 0)
{
ret = nand_sb_slc_is_block_bad(blk);
if (ret == 0)
{
while(page < nandgeom.pages_per_block)
{
sector = nand_bp_to_sector(blk, page);
nand_sb_slc_read_sector(sector, tmpbuff,NULL);
for (idx = 0; idx < 512; idx++)
{
*p8 = tmpbuff [idx];
p8++;
}
page++;
toread = toread - 512;
}
blk++;
page = 0;
}
else
{
blk++;
}
}
#ifdef USE_MMU
dcache_flush();
dcache_inval();
icache_inval();
#endif
execa();
}
