static void mainboard_enable(device_t dev)
{
dev->ops->init = &mainboard_init;
/* set up dcache and MMU */
/* FIXME: this should happen via resource allocator */
exynos5250_config_l2_cache();
mmu_init();
mmu_config_range(0, DRAM_START, DCACHE_OFF);
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
dcache_invalidate_all();
dcache_mmu_enable();
/* this is going to move, but we must have it now and we're
* not sure where */
exception_init();
const unsigned epll_hz = 192000000;
const unsigned sample_rate = 48000;
const unsigned lr_frame_size = 256;
clock_epll_set_rate(epll_hz);
clock_select_i2s_clk_source();
clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size);
power_enable_xclkout();
}
void setup_mmu(enum dram_state dram)
{
dcache_mmu_disable();
/* start with mapping everything as strongly ordered. */
mmu_config_range(0, 4096, DCACHE_OFF);
/* Map Device memory. */
mmu_config_range_kb(RPM_START, RPM_SIZE, DCACHE_OFF);
mmu_config_range_kb(SRAM_START, SRAM_END - SRAM_START,
DCACHE_WRITEBACK);
/* Map DRAM memory */
setup_dram_mappings(dram);
mmu_disable_range(DRAM_END, 4096 - DRAM_END);
/* disable Page 0 for trapping NULL pointer references. */
mmu_disable_range_kb(0, 1);
mmu_init();
dcache_mmu_enable();
}
static void enable_cache(void)
{
mmu_init();
/* Whole space is uncached. */
mmu_config_range(0, 4096, DCACHE_OFF);
/* SRAM is cached. MMU code will round size up to page size. */
mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB),
DCACHE_WRITEBACK);
mmu_disable_range(0, 1);
dcache_mmu_enable();
}
static void __attribute__((noinline)) romstage(void)
{
timestamp_init(0);
timestamp_add_now(TS_START_ROMSTAGE);
console_init();
exception_init();
sdram_init(get_sdram_config());
/* used for MMU and CBMEM setup, in MB */
u32 dram_start_mb = (uintptr_t)_dram/MiB;
u32 dram_end_mb = sdram_max_addressable_mb();
u32 dram_size_mb = dram_end_mb - dram_start_mb;
configure_l2_cache();
mmu_init();
/* Device memory below DRAM is uncached. */
mmu_config_range(0, dram_start_mb, DCACHE_OFF);
/* SRAM is cached. MMU code will round size up to page size. */
mmu_config_range((uintptr_t)_sram/MiB, div_round_up(_sram_size, MiB),
DCACHE_WRITEBACK);
/* DRAM is cached. */
mmu_config_range(dram_start_mb, dram_size_mb, DCACHE_WRITEBACK);
/* A window for DMA is uncached. */
mmu_config_range((uintptr_t)_dma_coherent/MiB,
_dma_coherent_size/MiB, DCACHE_OFF);
/* The space above DRAM is uncached. */
if (dram_end_mb < 4096)
mmu_config_range(dram_end_mb, 4096 - dram_end_mb, DCACHE_OFF);
mmu_disable_range(0, 1);
dcache_mmu_enable();
/*
* A watchdog reset only resets part of the system so it ends up in
* a funny state. If that happens, we need to reset the whole machine.
*/
if (power_reset_status() == POWER_RESET_WATCHDOG) {
printk(BIOS_INFO, "Watchdog reset detected, rebooting.\n");
hard_reset();
}
/* FIXME: this may require coordination with moving timestamps */
cbmem_initialize_empty();
early_mainboard_init();
run_ramstage();
}
void bootblock_soc_init(void)
{
rkclk_init();
mmu_init();
/* Start with a clean slate. */
mmu_config_range(0, 4096, DCACHE_OFF);
/* SRAM is tightly wedged between registers, need to use subtables. Map
* write-through as equivalent for non-cacheable without XN on A17. */
mmu_config_range_kb((uintptr_t)_sram/KiB,
_sram_size/KiB, DCACHE_WRITETHROUGH);
dcache_mmu_enable();
rkclk_configure_crypto(148500*KHz);
}
void bootblock_soc_init(void)
{
if (get_wakeup_state() == WAKEUP_DIRECT) {
wakeup();
/* Never returns. */
}
/* set up dcache and MMU */
mmu_init();
mmu_disable_range(0, SRAM_START);
mmu_config_range(SRAM_START, SRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range(SRAM_END, 4096 - SRAM_END, DCACHE_OFF);
dcache_mmu_enable();
/* For most ARM systems, we have to initialize firmware media source
* (ex, SPI, SD/MMC, or eMMC) now; but for Exynos platform, that is
* already handled by iROM so there's no need to setup again.
*/
}
static void mainboard_enable(device_t dev)
{
dev->ops->init = &mainboard_init;
/* set up dcache and MMU */
/* FIXME: this should happen via resource allocator */
exynos5250_config_l2_cache();
mmu_init();
mmu_config_range(0, DRAM_START, DCACHE_OFF);
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range((uintptr_t)_dma_coherent/MiB,
_dma_coherent_size/MiB, DCACHE_OFF);
mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
dcache_mmu_enable();
const unsigned epll_hz = 192000000;
const unsigned sample_rate = 48000;
const unsigned lr_frame_size = 256;
clock_epll_set_rate(epll_hz);
clock_select_i2s_clk_source();
clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size);
power_enable_xclkout();
}
/* this happens after cpu_init where exynos resources are set */
static void mainboard_init(device_t dev)
{
int dp_tries;
struct s5p_dp_device dp_device = {
.base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE,
.video_info = &dp_video_info,
};
void *fb_addr = (void *)(get_fb_base_kb() * KiB);
gpio_init();
i2c_init(TPS65090_BUS, I2C_0_SPEED, I2C_SLAVE);
i2c_init(7, I2C_0_SPEED, I2C_SLAVE);
tmu_init(&exynos5250_tmu_info);
/* Clock Gating all the unused IP's to save power */
clock_gate();
/* Disable USB3.0 PLL to save 250mW of power */
disable_usb30_pll();
set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr);
lcd_vdd();
// FIXME: should timeout
do {
udelay(50);
} while (!exynos_dp_hotplug());
exynos_dp_bridge_setup();
for (dp_tries = 1; dp_tries <= MAX_DP_TRIES; dp_tries++) {
exynos_dp_bridge_init();
if (exynos_dp_hotplug()) {
exynos_dp_reset();
continue;
}
if (dp_controller_init(&dp_device))
continue;
udelay(LCD_T3_DELAY_MS * 1000);
backlight_vdd();
backlight_pwm();
backlight_en();
/* if we're here, we're successful */
break;
}
if (dp_tries > MAX_DP_TRIES)
printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__);
// Uncomment to get excessive GPIO output:
// gpio_info();
}
static void mainboard_enable(device_t dev)
{
dev->ops->init = &mainboard_init;
/* set up dcache and MMU */
/* FIXME: this should happen via resource allocator */
exynos5250_config_l2_cache();
mmu_init();
mmu_config_range(0, DRAM_START, DCACHE_OFF);
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
dcache_invalidate_all();
dcache_mmu_enable();
/* this is going to move, but we must have it now and we're
* not sure where */
exception_init();
const unsigned epll_hz = 192000000;
const unsigned sample_rate = 48000;
const unsigned lr_frame_size = 256;
clock_epll_set_rate(epll_hz);
clock_select_i2s_clk_source();
clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size);
power_enable_xclkout();
}
