static void dce_disp_clk_construct(
struct dce_disp_clk *clk_dce,
struct dc_context *ctx,
const struct dce_disp_clk_registers *regs,
const struct dce_disp_clk_shift *clk_shift,
const struct dce_disp_clk_mask *clk_mask)
{
struct display_clock *base = &clk_dce->base;
base->ctx = ctx;
base->funcs = &dce_funcs;
clk_dce->regs = regs;
clk_dce->clk_shift = clk_shift;
clk_dce->clk_mask = clk_mask;
clk_dce->dfs_bypass_disp_clk = 0;
clk_dce->dprefclk_ss_percentage = 0;
clk_dce->dprefclk_ss_divider = 1000;
clk_dce->ss_on_dprefclk = false;
base->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
base->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
dce_clock_read_integrated_info(clk_dce);
dce_clock_read_ss_info(clk_dce);
dce_divider_range_construct(
&clk_dce->divider_ranges[DIVIDER_RANGE_01],
DIVIDER_RANGE_01_START,
DIVIDER_RANGE_01_STEP_SIZE,
DIVIDER_RANGE_01_BASE_DIVIDER_ID,
DIVIDER_RANGE_02_BASE_DIVIDER_ID);
dce_divider_range_construct(
&clk_dce->divider_ranges[DIVIDER_RANGE_02],
DIVIDER_RANGE_02_START,
DIVIDER_RANGE_02_STEP_SIZE,
DIVIDER_RANGE_02_BASE_DIVIDER_ID,
DIVIDER_RANGE_03_BASE_DIVIDER_ID);
dce_divider_range_construct(
&clk_dce->divider_ranges[DIVIDER_RANGE_03],
DIVIDER_RANGE_03_START,
DIVIDER_RANGE_03_STEP_SIZE,
DIVIDER_RANGE_03_BASE_DIVIDER_ID,
DIVIDER_RANGE_MAX_DIVIDER_ID);
}
struct clk_mgr *dcn1_clk_mgr_create(struct dc_context *ctx)
{
struct dc_debug_options *debug = &ctx->dc->debug;
struct dc_bios *bp = ctx->dc_bios;
struct dc_firmware_info fw_info = { { 0 } };
struct dce_clk_mgr *clk_mgr_dce = kzalloc(sizeof(*clk_mgr_dce), GFP_KERNEL);
if (clk_mgr_dce == NULL) {
BREAK_TO_DEBUGGER();
return NULL;
}
clk_mgr_dce->base.ctx = ctx;
clk_mgr_dce->base.funcs = &dcn1_funcs;
clk_mgr_dce->dfs_bypass_disp_clk = 0;
clk_mgr_dce->dprefclk_ss_percentage = 0;
clk_mgr_dce->dprefclk_ss_divider = 1000;
clk_mgr_dce->ss_on_dprefclk = false;
clk_mgr_dce->dprefclk_khz = 600000;
if (bp->integrated_info)
clk_mgr_dce->dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
if (clk_mgr_dce->dentist_vco_freq_khz == 0) {
bp->funcs->get_firmware_info(bp, &fw_info);
clk_mgr_dce->dentist_vco_freq_khz = fw_info.smu_gpu_pll_output_freq;
if (clk_mgr_dce->dentist_vco_freq_khz == 0)
clk_mgr_dce->dentist_vco_freq_khz = 3600000;
}
if (!debug->disable_dfs_bypass && bp->integrated_info)
if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
clk_mgr_dce->dfs_bypass_enabled = true;
dce_clock_read_ss_info(clk_mgr_dce);
return &clk_mgr_dce->base;
}